Data caching system and data caching method

A technology of data caching and Ethernet, which is applied in the direction of digital transmission system, transmission system, data exchange network, etc., can solve the problem of poor scalability of data caching, and achieve high scalability, high scalability, and high bandwidth utilization Effect

Active Publication Date: 2014-05-07
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0026] In order to solve the problem of poor scalability of data cache in the prior art, the present invention provides a general data cache system and method

Method used

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  • Data caching system and data caching method
  • Data caching system and data caching method

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Embodiment Construction

[0051] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0052] figure 1 It is a structural block diagram of the general data cache system of the present invention, which specifically includes:

[0053] Input packet processing device IPC 101 (Input Package Process): IPC receives Ethernet data frames from several external high-speed interfaces, and completes bit width conversion and frame format conversion; it includes:

[0054] Bit width converter BC (Bit Convertor): Multiple independent BC devices receive data packets input from different Ethernet interfaces such as XGMII, XLGMII, CGMII, etc., and detect the SOP (StartOf Package) control word of the data packet, EOP (EndOfPackage). Of Package) control word, and perform bit width conversion on mes...

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Abstract

The invention discloses a data caching system used for Ethernet equipment. The data caching system comprises an input data packet processing device IPC, a cache address managing device PMG, a cache read-write managing device MCT, and an output data packet processing device OPC. The input data packet processing device IPC is used for receiving data frames from multiple Ethernet interfaces and converting received Ethernet data frames into data with uniform bit widths and packaged formats. The cache address managing device PMG is used for maintaining cache addresses in which data has been written and current idle cache addresses. The cache read-write managing device MCT is used for generating a read instruction or write instruction according to the Ethernet data frames received by the IPC and the current idle cache addresses maintained by the PMG. The output data packet processing device OPC is used for performing bit width conversion and format packaging on the data read by the MCT and outputting the data via a corresponding Ethernet interface. Additionally, the invention also discloses a data caching method used for Ethernet equipment. The data caching system and the data caching method support multiple Ethernet interfaces and resolve a problem of poor expandability of a conventional caching scheme.

Description

technical field [0001] The invention relates to the field of data cache, in particular to a data cache system and method for Ethernet equipment. Background technique [0002] Some English abbreviations and their explanations used in this article: [0003] RAM: random access memory, random access memory [0004] SRAM: Static RAM static random access memory [0005] SDRAM: Synchronous Dynamic RAM, synchronous dynamic random access memory [0006] MAC: Medium Access Control, medium access control layer [0007] DDR: Double Data Rate double rate synchronous dynamic random access memory [0008] QDR: Quad Data Rate, 4 times data magnification [0009] FCS: frame check sequence, frame check sequence [0010] CRC: Cyclical Redundancy Check, cyclic redundancy check [0011] FIFO: First Input First Output, first in first out queue [0012] FPGA: Field Programmable Gate Array, Field Programmable Gate Array [0013] ASIC: Application Specific Integrated Circuit, application sp...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/861H04L49/901
CPCH04L49/901H04L49/351H04L61/58H04L47/6245
Inventor 袁峰
Owner SANECHIPS TECH CO LTD
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