Slew rate enhancement circuit applicable to LDO regulators (low dropout regulators)
A slew rate enhancement, circuit technology, applied in the direction of regulating electrical variables, control/regulating systems, instruments, etc., can solve problems such as low quiescent current and fast load transient response, and achieve increased slew rate, improved transient response, The effect of improving output accuracy
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[0023] Such as figure 2 As shown, a slew rate enhancement circuit applied to LDO includes PMOS tube M 0 , M 2 , M 4 , M 6 , M 8 , NMOS tube M 1 , M 3 , M 5 , M 7 , M 9 and capacitance C f ; The capacitance C f One end is the input end of the slew rate enhancement circuit, and the other end is connected to the PMOS transistor M 2 The gate, drain, PMOS transistor M 4 The gate, PMOS transistor M 6 The gate and NMOS tube M 3 the drain connection;
[0024] PMOS tube M 2 The sources are connected with the PMOS transistor M 0 The source, PMOS transistor M 4 The source, PMOS transistor M 6 The source, PMOS transistor M 8 The source is connected, and connected to the external input power supply V IN , PMOS tube M 2 The drain is connected to the NMOS transistor M 3 The drain of the PMOS tube M 2 The gate is connected to the PMOS transistor M4 grid;
[0025] PMOS tube M 4 The drain of the NMOS transistor M 5 The drain and NMOS transistor M 9 connected to the g...
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