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Integrated circuit floor planning method based on moving modal sequence and Memetic algorithm

A mobile pattern sequence, integrated circuit technology, applied in the direction of genetic model, can solve the problems of poor stability, slow convergence, unable to obtain project schedule and other problems, achieve good implicit parallelism, ensure effective search, and avoid local optimality. Effect

Active Publication Date: 2014-04-09
XIDIAN UNIV
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AI Technical Summary

Problems solved by technology

Therefore, only using the genetic algorithm to solve the layout problem cannot imitate the intelligence of biological processing things well. In addition, the genetic algorithm has the disadvantages of premature convergence, slow convergence speed, poor stability, etc., so that a good project schedule cannot be obtained.

Method used

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  • Integrated circuit floor planning method based on moving modal sequence and Memetic algorithm
  • Integrated circuit floor planning method based on moving modal sequence and Memetic algorithm
  • Integrated circuit floor planning method based on moving modal sequence and Memetic algorithm

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Embodiment Construction

[0058] The layout method studied by the present invention is to determine the position of the hard module on the chip, so that certain performances of the chip, such as the chip area and the total length of interconnection lines between modules, can be optimized. The present invention solves how to place modules, and aims at minimizing the area of ​​the chip, and tests the standard question bank MCNC Benchmark.

[0059] Such as figure 2 as shown,

[0060] The main flowchart step features are:

[0061] Step 101: start parameter setting, N is the number of populations in the genetic algorithm, M is the number of individuals in each population, H is a constant (here set to 100), which is used to divide by the cost value of each individual area, so that Get the individual fitness. RX and RY respectively represent the maximum value of the abscissa and the maximum value of the ordinate in the two-dimensional plane where the rectangular module is placed. T represents the number ...

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Abstract

The invention relates to an integrated circuit floor planning method based on a moving modal sequence and a Memetic algorithm. The integrated circuit floor planning method based on the moving modal sequence and the Memetic algorithm is characterized by comprising the steps that the widths, the heights, the moving modes and the rotating modes of individuals in a group are initialized, and the size cost and the fitness of each individual are calculated by using the method of the moving modal sequence; a selection operator of a genetic algorithm is applied, tabu searching is used for carrying out local searching, and a crossover operator and a mutation operator are used. It is certain that after the module sequence, the moving mode and the rotating mode are changed each time, the fitness of each individual needs to be calculated again through the method of the moving modal sequence. The integrated circuit floor planning method based on the moving modal sequence and the Memetic algorithm has the advantages of being capable of solving a very large scale integration, and also capable of expanding to solution of other combinational optimization problems.

Description

technical field [0001] The present invention relates to physical design layout planning, in particular to an integrated circuit layout method based on moving modal sequence (MMS) and genetic taboo (Memetic algorithm). Background technique [0002] Floorplanning is a key link in the physical design of very large scale integration (VLSI), and its results have an important impact on the final chip size and global interconnection structure. With the rapid development of technology, the complexity of chip design is increasing rapidly, and the requirements for chip size and internal interconnection performance are also getting higher and higher, which makes the role of layout planning particularly important. For the floorplanning problem, many scholars have proposed a variety of algorithms using different mathematical tools, including the minimum partition algorithm, hierarchical design method, analytical algorithm and stochastic optimization algorithm. The basic operation of the...

Claims

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Application Information

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IPC IPC(8): G06N3/12
Inventor 刘静焦李成韩二丽朱园马文萍马晶晶
Owner XIDIAN UNIV
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