Planar VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) transistor and preparation method thereof

Abstract

The invention provides a planar VDMOS (Vertical Double-Diffusion Metal-Oxide-Semiconductor) transistor and a preparation method thereof and belongs to the field of VDMOS transistor devices. The planar VDMOS transistor comprises a substrate, an epitaxial layer, a body region, a source region, a gate dielectric layer and a gate electrode, wherein the epitaxial layer is formed on the substrate, the body region and the source region are formed in the epitaxial layer, and the gate dielectric layer is formed on the epitaxial layer. One or more grooves basically parallel to the channel direction of the planar VDMOS transistor are formed in the upper surface of part, of the epitaxial layer, corresponding to the gate dielectric layer, and the corresponding part, of the gate dielectric layer, above the grooves is correspondingly sunken to form a concave-convex gate dielectric layer. The planar VDMOS transistor has the characteristics of small on resistance, and small loss and no electromagnetic interference during switching application.

Description

technical field [0001] The invention belongs to the field of VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor, vertical double-diffused metal-oxide-semiconductor) transistor devices, and relates to a planar VDMOS transistor with a concave-convex gate dielectric layer and a preparation method thereof. Background technique [0002] DMOS (Double-diffused Metal-Oxide-Semiconductor, double-diffused metal-oxide-semiconductor) transistor is a kind of MOSFET, which has the characteristics of high power and high breakdown voltage, and is one of the common power devices. Generally, according to the orientation of the drift region in DMOS relative to the substrate surface, it can be divided into lateral DMOS (LDMOS) and VDMOS transistors; VDMOS transistors further include trench VDMOS transistors and planar VDMOS transistors. [0003] figure 1 Shown is a schematic diagram of a three-dimensional cell structure of a traditional planar VDMOS transistor. like figure 1 As shown,...

AI Technical Summary

Problems solved by technology

However, the applicant found that if the loss of the planar VDMOS transistor is too high and the switching speed is too fast, it is easy to cause electromagnetic interference problems in the switching circuit

Images