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Shallow groove isolation structure and manufacturing method thereof

A shallow trench and trench technology, applied in semiconductor/solid-state device manufacturing, electrical components, transistors, etc., can solve the problems of device influence, limited stress, device current leakage, etc. effect on device performance

Active Publication Date: 2014-03-26
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Usually amorphous dielectric materials (such as Si 3 N 4 ) may contain many charges, which may negatively affect the device
In current process flows that use dielectrics as isolation materials, such as during etch and clean processes such as forming gate oxides or gate stacks, there may be gaps between the active area and the filled isolation trenches ( divot, or change in topography due to loss of material), a phenomenon that can cause device current leakage and other problems
Additionally, the use of an amorphous dielectric as the isolation material allows for limited stress introduction into the channel

Method used

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  • Shallow groove isolation structure and manufacturing method thereof
  • Shallow groove isolation structure and manufacturing method thereof
  • Shallow groove isolation structure and manufacturing method thereof

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Embodiment Construction

[0016] One or more aspects of embodiments of the invention are described below with reference to the drawings, wherein like reference numerals generally refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects of the embodiments of the invention. It may be apparent, however, to one skilled in the art that one or more aspects of the embodiments of the invention may be practiced with a lesser degree of these specific details.

[0017] In addition, although a particular feature or aspect of an embodiment is disclosed in terms of only one of some implementations, such feature or aspect may be combined with other implementations that may be desirable and advantageous for any given or particular application. One or more other features or aspects of .

[0018] first provide as figure 1 A semiconductor substrate 100 is shown. The substrate...

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Abstract

The invention relates to a shallow groove isolation structure and a manufacturing method thereof. The method comprises the following steps: providing a semiconductor substrate; forming at least one groove in the semiconductor substrate; filling the grooves with stressed metal or submetallic oxide thereof; converting the metal or submetallic oxide into a metal oxide dielectric medium. According to the method, the crystal metal oxide dielectric medium, instead of an amorphous dielectric medium, is adopted to serve as an isolating material of the shallow groove isolation structure, so that the device performance is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a shallow trench isolation structure and a manufacturing method thereof. Background technique [0002] In conventional shallow trench isolation (STI) use such as SiO 2 、Si 3 N 4 The dielectric acts as an isolation material between devices. Usually amorphous dielectric materials (such as Si 3 N 4 ) may contain many charges, which may negatively affect the device. In current process flows that use dielectrics as isolation materials, such as during etch and clean processes such as forming gate oxides or gate stacks, there may be gaps between the active area and the filled isolation trenches ( divot, or change in shape due to loss of material), a phenomenon that can cause device current leakage, among other problems. Additionally, the use of an amorphous dielectric as the isolation material allows for limited introduction of stress into the channel. [000...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762H01L27/092
CPCH01L21/76227
Inventor 钟汇才赵超梁擎擎
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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