Very large scale integration (VLSI) standard unit overall arranging method based on L1 form model

Abstract

The invention relates to a very large scale integration (VLSI) standard unit overall arranging method based on an L1 form model and belongs to the technical field of VLSI physical design automation. The method includes indicating a circuit as a super graph, modeling a VLSI standard unit overall arranging problem which adopts semi-cycle long-line calculation with the density constrained to be non-smooth into an L1 form minimum problem, adopting an optimum selection clustering algorithm applicable to modification of an L1 form model in a clustering stage to conduct clustering on a unit and conducting declustering on clusters in a declustering stage by adopting a nonlinear planning overall arranging method. The VLSI standard unit overall arranging method is reasonable in arrangement, high in efficiency, practical and good in arranging effect.

Description

technical field [0001] The invention relates to a global layout method of VLSI standard cells based on an L1 norm model, and belongs to the technical field of VLSI physical design automation. Background technique [0002] In the current VLSI layout, the scale of integrated circuits continues to increase and the requirements for technology are getting higher and higher, which puts forward higher requirements for the optimization goals and optimization methods of VLSI layout. The quality of the layout results directly affects the quality of the entire chip. performance. With the rapid growth of the number of units on a chip, especially the widespread application of millions of gate chips, it poses a huge challenge to the automation of VLSI layout design. Therefore, it is of great significance to seek more efficient and practical integrated circuit layout algorithms. [0003] Algorithms used to solve VLSI placement problems can be divided into the following three categories: ...

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Problems solved by technology

[0005] However, there are two following problems in the existing global layout methods based on analytical methods: (1) in the global layout process, some approximate model (such as quadratic model, LSE model, Bound2bound model, etc.), so there is a large error in the bus length calculated after the approximation and the bus length of the sum of the half-perimeter line length, which is not a good reflection of the actual line length of the layout, so the quality of the layout cannot be guaranteed; (2 ) The density constraint function is non-smooth, and the existing layout algorithms using density control technology will D b ( x , y ) for smoothing

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