Forming method for multiple graphical mask layer and semiconductor structure

Abstract

The invention relates to a forming method for a multiple graphical mask layer and a semiconductor structure. The forming method for the multiple graphical mask layer includes the steps that a semiconductor substrate is provided, and a material layer to be etched is formed on the semiconductor substrate; a plurality of discrete stack structures are formed on the surface of the material layer to be etched, and the stack structures comprise sacrificial layers and first mask layers located on the surfaces of the sacrificial layers; part of the sacrificial layers are etched back along the two sides of the stack structures, so that the profile image of the stack structures is in a T type; a second mask layer is formed on the surface of the material layer to be etched and covers the surfaces and the lateral walls of the T-type stack structures; the second mask layer is etched, and side walls are formed on the lateral walls of the sacrificial layers below the first mask layers of the T-type stack structures; the first mask layers and the sacrificial layers are removed, and the side walls are the multiple graphical mask layer. The side wall is formed on the lateral walls of the sacrificial layers of the T-type stack structures, so that morphology difference between lateral walls on the two sides of the side walls is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a multi-patterned mask layer and a semiconductor structure. Background technique [0002] In the field of semiconductor manufacturing, photoresist materials are used to transfer mask images to one or more material layers, for example, transfer mask images to metal layers, dielectric layers or semiconductor substrates. However, as the feature size of the semiconductor process continues to shrink, it becomes more and more difficult to form a mask pattern with a small feature size in the material layer by using a photolithography process. [0003] In order to improve the integration level of semiconductor devices, various double patterning processes have been proposed in the industry, among which the self-aligned double patterning (Self-Aligned Double Patterning, SADP) process is one of them. The US patent document with the publication number US2009 / 0...

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Problems solved by technology

[0008] However, after using the self-aligned double pattern as a mask to etch the material layer 20 to be etched, the morphology of the sidewalls on both sides of the semiconductor pattern 21 formed at the bottom of the sidewall 45 will be different, which will affect the subsequent formation. The performance of semiconductor devices

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