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Control flow graph reconstruction method for scheduled assembly codes

A control flow graph and scheduling technology, applied in program control design, program control devices, instruments, etc., can solve problems such as low efficiency

Inactive Publication Date: 2014-02-12
INST OF ACOUSTICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method introduces more extra instructions when solving the de-delay slot operation of multi-cycle instructions, and the efficiency is low

Method used

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  • Control flow graph reconstruction method for scheduled assembly codes
  • Control flow graph reconstruction method for scheduled assembly codes
  • Control flow graph reconstruction method for scheduled assembly codes

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Embodiment Construction

[0026] The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0027] figure 1 It is a flowchart of a method for reconstructing a control flow graph of scheduled assembly code in an embodiment of the present invention. Such as figure 1 As shown, embodiments of the present invention include:

[0028] Step 110, perform static analysis on the source program, and obtain all possible execution paths of the source program according to the information of the global delay slot list, thereby constructing an instruction flow graph; wherein, each node in the instruction flow graph represents an instruction, and each An edge represents a possible execution order relationship from one instruction to another.

[0029] Only the branch instruction in the instruction set affects the control direction of the program. For a specific target architecture, there is a certain number of delay slots f...

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Abstract

The invention relates to a control flow graph reconstruction method for scheduled assembly codes. The method includes the steps that static analysis is carried out on a source program, all possible execution paths of the source program are obtained through global delay slot list information, and an instruction flow graph is built; each node in the instruction flow graph represents one instruction; all nodes in the instruction flow graph are traversed, basic blocks are built according to in-degree information and out-degree information of each node, and a control flow graph is built; on the basis of the control flow graph, each execution packet in each basic block is analyzed, and an assembly level data dependence graph is built for the execution packets; according to information of a source system structure instruction set, timestamp information of each instruction in each execution packet is determined; according to the timestamp information of each instruction, cross-block or cross-packet moving of the instructions is carried out; according to the assembly level data dependence graph, the timestamp information of each instruction is modified; according to the modified timestamp information of each instruction, the instructions are sequenced again, and therefore equivalent execution of the instructions in the source program is restored.

Description

technical field [0001] The invention relates to the field of digital data processing, in particular to a control flow graph reconstruction method for scheduled assembly codes. Background technique [0002] In the field of digital signal processors, a lot of software is implemented in the form of compilation for specific target architecture features. These software are difficult to understand and maintain, and it is not easy to complete the transplantation between different architectures. In the field of reverse engineering and binary translation, the first step to complete these tasks is to reconstruct the control flow of the source assembler. [0003] In the field of compiler design, many code optimization techniques are directly aimed at the assembly code, mainly including: link-time program global analysis and optimization, code compression, binary translation, etc. These optimization techniques are all completed based on the control flow graph (Control Flow Graph, CFG)...

Claims

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Application Information

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IPC IPC(8): G06F9/45G06F9/44
Inventor 应欢王雷欧王东辉洪缨
Owner INST OF ACOUSTICS CHINESE ACAD OF SCI
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