Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

AES (advanced encryption standard) algorithm circuit oriented method for testing differential power attack

A differential power consumption attack and testing method technology, which is applied in computing, electrical digital data processing, special data processing applications, etc., can solve the problems of poor reliability, low reliability of results, and difficult implementation, etc. Design, shorten the design cycle, optimize the effect of the design process

Inactive Publication Date: 2014-01-22
SOUTHEAST UNIV
View PDF2 Cites 20 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Some scholars use the simulation attack method designed by mathematical modeling. Although the attack is efficient and the cost is low, its accuracy is very low, the reliability of the result is not high, and it is not suitable for verifying the anti-power analysis characteristics of the cryptographic algorithm circuit.
[0007] To sum up, in the prior art, the power consumption attack method for cryptographic algorithm circuits implemented by FPGA and ASIC has the defects of high cost, difficult implementation, and long verification cycle, and the simulation attack method designed by mathematical modeling has low precision. , the defect of poor reliability

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • AES (advanced encryption standard) algorithm circuit oriented method for testing differential power attack
  • AES (advanced encryption standard) algorithm circuit oriented method for testing differential power attack
  • AES (advanced encryption standard) algorithm circuit oriented method for testing differential power attack

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0036] The present invention will be further described below in conjunction with the drawings and specific embodiments.

[0037] Such as figure 1 Shown is the overall framework of the differential power attack test method for AES algorithm circuits of the present invention. The core of the AES cryptographic algorithm circuit power attack test method has three parts: functional simulation module, power consumption simulation module and power analysis module. The basic process is to first use the RTL code of the algorithm to synthesize the circuit netlist file through the DC (AESign Compiler, DC) tool, and then load the test vector necessary for the netlist such as plaintext and clock, and the standard cell library and timing parameters used by the netlist Simulate through VCS together to generate functional simulation waveforms. Functional simulation waveforms need to be converted into VCD files for power consumption simulation analysis. Then set the PTPX simulation environment...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an AES (advanced encryption standard) algorithm circuit oriented method for testing differential power attack. An AES algorithm is a widely applied grouping symmetric cryptographic algorithm. The AES algorithm circuit oriented method is used for acquiring and processing power samples for tests for the differential power attack in a design stage of an AES cryptographic algorithm circuit and includes steps (1), carrying out functional simulation and acquiring power samples; (2), preprocessing the power samples; (3), acquiring hypothetical power samples; (4), computing correlation coefficients and analyzing attack results. The AES algorithm circuit oriented method has the advantages that only varied power points are sampled, so that large quantities of power sample data can be omitted, power attack computational complexity can be greatly reduced, the assess effectiveness and the speed are high, more importantly, the tests for the differential power attack can be carried out in the design stage of the circuit, the attack resistance of the cryptographic circuit can be assessed in advance, and tape-out risks of the AES circuit can be reduced.

Description

Technical field [0001] The invention relates to the field of information security of integrated circuits, in particular to a differential power consumption attack test method for AES algorithm circuits. Background technique [0002] In the 21st century, the rapid development of science and technology, social informatization has become the general trend, life has become informatized, digitized and networked, and people's dependence on information is increasing. With the development of computer, network, communication technology and integrated circuit technology, security chips are widely used in automatic teller machines (Automatic Teller Machine, ATM) bank cards, smart cards for access control systems in residential or company environments, and voice encryption chips in mobile phones In various environments that require information security. Because the circuit structure inside the integrated circuit is very complicated, it also has the characteristics of good sealing, not easy ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 单伟伟孙华芳王学香
Owner SOUTHEAST UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products