Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Differential power attack testing method for DES (data encryption standard) algorithm circuit

A technology of differential power consumption attack and testing method, which is applied in the direction of electrical components, encryption devices with shift registers/memory, digital transmission systems, etc. It can solve the problem of anti-power consumption analysis characteristics of circuits that are not suitable for verifying cryptographic algorithms, and the results are credible Problems such as low precision and long verification cycle, etc., achieve the effect of shortening the design cycle, saving storage space, and fast speed

Inactive Publication Date: 2014-01-22
SOUTHEAST UNIV
View PDF1 Cites 18 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Some scholars use the simulation attack method designed by mathematical modeling. Although the attack is efficient and the cost is low, its accuracy is very low, the reliability of the result is not high, and it is not suitable for verifying the anti-power analysis characteristics of the cryptographic algorithm circuit.
[0007] To sum up, in the prior art, the power consumption attack method for cryptographic algorithm circuits implemented by FPGA and ASIC has the defects of high cost, difficult implementation, and long verification cycle, and the simulation attack method designed by mathematical modeling method has low precision. , the defect of poor reliability

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Differential power attack testing method for DES (data encryption standard) algorithm circuit
  • Differential power attack testing method for DES (data encryption standard) algorithm circuit
  • Differential power attack testing method for DES (data encryption standard) algorithm circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0038] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0039] Such as figure 1 Shown is the process of obtaining power consumption samples in the present invention. First, set the working environment of the encryption algorithm circuit, that is, load a series of test vectors, such as clock, IO stimulus, random plaintext and key input, etc. The invention adopts VCS to carry out function simulation on the net list circuit of DES, and generates VPD (Vcd Plus Deltacycleon, VPD) file after the simulation is finished. This file contains the changes of various internal standard units during the operation of the encryption algorithm. The VPD file is then converted to a VCD file for use by the Power Consumption Simulation Module. The tool used by the power consumption simulation module is the PTPX tool of Synopsys Company. Properly configure PTPX, combined with the power consumption model of the cell li...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a differential power attack testing method for a DES algorithm circuit. A DES algorithm is a widely-applied grouping symmetric encryption algorithm. According to the method, a differential power attack test is performed on the DES algorithm circuit at a design stage, and the method comprises the steps as follows: (1), functional simulation and acquisition of a power consumption sample; (2), preprocessing of the power consumption sample; (3), acquisition of a hypothetical power consumption sample; and (4) calculation of correlation coefficients and analysis of attack results. According to the differential power attack testing method, only varying power consumption points are sampled, a large number of power consumption sample data are saved, the power attack calculation amount is reduced substantially, the method has the advantages of high evaluation efficiency and high speed, and above all, the power attack test can be performed at the circuit design stage, so that the anti-attack capability of a password circuit is evaluated in advance, and the redesign risk of the DES circuit after assembly line production of chips is reduced.

Description

technical field [0001] The invention relates to the field of information security of integrated circuits, in particular to a differential power consumption attack test method of a DES cryptographic algorithm circuit. Background technique [0002] Entering the 21st century, with the rapid development of science and technology, social informatization has become the general trend, life has become informatized, digitized and networked, and people's dependence on information is constantly increasing. With the development of computer, network, communication technology and integrated circuit technology, security chips are widely used in various needs such as new generation IC (integrated circuit) bank cards, smart cards for access control systems in residential or corporate environments, and voice encryption chips in mobile phones. in an information security environment. Because the circuit structure inside the integrated circuit is very complex, and it has the characteristics of ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H04L29/06H04L9/06H04L12/26
Inventor 单伟伟孙华芳王学香徐志鹏
Owner SOUTHEAST UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products