Manufacturing method of semiconductor device with silicon germanium doped region

Abstract

The invention provides a manufacturing method of a semiconductor device with a silicon-germanium doped zone. The method comprises steps of: forming an etching barrier layer on the top surface of a gate electrode; forming sequentially a side wall of the gate electrode on a gate-electrode sidewall; covering the gate electrode and a semiconductor substrate with a sacrificial barrier layer; forming between the second step and the third step a protection oxide layer, located outside the gate-electrode sidewall of the side wall of the gate electrode, without shielding the etching barrier layer on the top surface of the gate electrode in order to remove the etching barrier layer on the top surface of the gate electrode together with the etching removing of the sacrificial barrier layer. Meanwhile, the protection oxide layer can effectively protect the side wall of the gate electrode from being damaged by etching, which thereby saves the technology step of removing the sacrificial barrier layer and improves the performance of the semiconductor device.

Description

technical field [0001] The invention relates to a manufacturing method of an integrated circuit, in particular to a manufacturing method of a semiconductor device capable of protecting a grid from etching damage during the formation of a silicon-germanium doped region. Background technique [0002] With the rapid development of semiconductor manufacturing technology, the size of semiconductor devices is getting smaller and more integrated, and millions or even more circuit elements can be formed on an integrated circuit wafer. In order to achieve higher component integration, the line width of semiconductor devices is continuously reduced, and the size of common metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field Oxide Transistor, MOSFET) must also be reduced. [0003] For semiconductor devices of 28nm level and below, silicon germanium doped regions are widely used. The silicon-germanium doped region is a silicon-germanium compound region fo...

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Problems solved by technology

However, when subsequent etching removes the etch barrier layer 15 and the sacrificial barrier layer 19, the nitride layer 18 and the etch barrier layer 15 located on the PMOS region 1 are firstly removed simultaneously, and then after the oxide layer 17 is removed, due to silicon oxide and silicon nitride in the etch rate are quite different, which will cause the residue of the etch barrier layer 15 on the top surface of the gate 13 of the NMOS region 2, thereby reducing the electrical connection performance of the gate 13 of the NMOS region 2. One-step etching to remove the etch barrier layer 15 in the NMOS region will etch and damage the gate 13 of the PMOS region 1 at the same time, reducing the electrical connection performance of the gate 13 in the PMOS region 1, thereby affecting the performance of the semiconductor device

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