Signal processing method and circuit and led dimming circuit with the circuit
A signal processing and signal technology, applied in the field of electronics, can solve the problems of slow circuit response, capacitors that cannot be integrated inside the chip, and miniaturized integrated circuits that cannot be realized.
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Embodiment 1
[0086] This embodiment provides a signal processing circuit, which mainly includes a sampling circuit 101 , a pulse count control circuit 102 , and a pulse width modulation signal generation circuit 103 .
[0087] Wherein, the input end of the sampling circuit 101 is connected to the first pulse width modulation signal and the first clock signal input from the outside, the output end is connected to the input end of the pulse count control circuit 102, and the output end of the pulse count control circuit 102 is connected to the pulse width modulation The input terminal of the signal generating circuit 103 is connected. Its circuit works as follows:
[0088] The sampling circuit 101 samples the first pulse width modulation signal according to the frequency of the first clock signal, obtains the sampling pulse, and obtains the number of sampling pulses corresponding to the high level within one cycle of the first pulse width modulation signal within the sampling pulse (hereina...
Embodiment 2
[0103] As a schematic illustration of the signal processing circuit of this embodiment, the following will schematically describe this embodiment with regard to the implementation manner of a specific application circuit of this embodiment.
[0104] see image 3 As shown, in this embodiment, the sampling circuit 301 can be composed of, but not limited to, the following circuit structure.
[0105] The sampling circuit 301 includes: a first counter 3011 , a second counter 3012 and a third counter 3013 . Wherein, the input terminals of the first counter 3011 are connected to the first pulse width modulation signal PMW1 and the first clock signal f1 respectively, and the output terminals are respectively connected to the signal input terminals of the second counter 3012 and the third counter 3013 . It works as follows:
[0106] The clock input terminal "CLK" of the first counter 3011 is connected to the first clock signal f1, and the clearing control terminal "CLR" is connected ...
Embodiment 3
[0129] see Figure 4 As shown, this embodiment provides a signal processing method, which mainly includes the following steps:
[0130] Step 401: Sampling the first PWM signal at a low frequency to obtain a sampling pulse.
[0131] According to the frequency of the first clock signal with a lower frequency, the first pulse width modulation signal is sampled to obtain a sampling pulse.
[0132] In the same way as in Embodiment 2, in this embodiment, three counters can also be used to sample the number of high-level sampling pulses and the number of low-level sampling pulses of the sampling pulses in a first pulse width modulation signal cycle. . For example, the cooperation process of three counters is as follows:
[0133] S1: The first counter samples the first pulse width modulation signal according to the frequency of the first clock signal, outputs the sampling pulse, and inputs the sampling pulse to the second counter and the third counter respectively.
[0134] S2: Th...
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