Anti-radiation hardening latch based on TMR and DICE

Abstract

The invention relates to the field of anti-radiation integrated circuit design in microelectronics, and provides an anti-radiation hardening latch based on TMR and a DICE. In order to achieve protection of SEU of internal data, according to the technical scheme, the anti-radiation hardening latch based on the TMR and the DICE is characterized in that an input satge is composed of four voting modules 1, 2, 3 and 4, the voting module 1 and the voting module 3 receive in-phase input signals, the voting module 2 and the voting module 4 receive anti-phase input signals, N-type transistors M1, M2, M3 and M4 are controlled by a clock signal CK, the voting modules 1, 2, 3 and 4 achieve voting on selecting one from the front-stage input signals A, B and C and the anti-phase signals of the front-stage input signals A, B and C, the communication condition of the voting module 1 is the same as that of the voting module 3, the communication condition of the voting module 2 is the same as that of the voting module 4, and the communication condition of the voting module 1 is opposite to that of the voting module 2. The anti-radiation hardening latch based on the TMR and the DICE is mainly applied to the anti-radiation integrated circuit design.

Description

Technical field [0001] The present invention relates to the field of radiation-resistant integrated circuit design in microelectronics, in particular to the application of redundancy technology to design the timing of radiation-resistant hardening for single event transient (SET) and single event upset (SEU) The circuit is a radiation-resistant hardened latch based on three-mode redundancy and DICE. technical background [0002] When the integrated circuit works in a space environment, the high-energy particles present in the environment will enter the chip and ionize the silicon along the incident trajectory, thereby generating a large number of electron-hole pairs. The ionized charge formed by these electron-hole pairs can interfere with the normal state of the nodes in the circuit. For combinational logic in digital circuits, the ionized charge generated by incident particles will produce a transient level jump at its output, called Single Event Transient (SET); for sequentia...

AI Technical Summary

Problems solved by technology

However, TMR itself introduces a large area and power overhead; the DICE structure cannot eliminate the SET occurring on the input port

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