Method for processing porous ultra-low dielectric constant layer

Abstract

The invention provides a method for processing a porous ultra-low dielectric constant layer. The method comprises the steps of providing a semiconductor device for a reaction cavity, wherein the surface of the semiconductor device is provided with the porous ultra-low dielectric constant layer, the temperature of the reaction cavity is 300-400 DEG C, and the pressure is 80-300 bar; leading a CO2 supercutical fluid solution into the reaction cavity, wherein tetramethyl divinyl disilazane is dissolved in the solution; and enabling the solution to be contacted with the porous ultra-low dielectric constant layer.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for processing a porous ultra-low dielectric constant layer. Background technique [0002] With the development of integrated circuit technology, the semiconductor industry has entered the sub-micron era. The ever-shrinking feature sizes and increasing metal trace aspect ratios lead to a rapid rise in interconnect capacitance, which in turn causes crosstalk issues. On the other hand, the increase in interlayer parasitic capacitance caused by the increase in the number of layers and additional interconnection delays have become the main obstacle to improving the circuit speed. Parasitic capacitance also increases power dissipation. All these problems limit the improvement of circuit performance. Finding and developing new low-k (dielectric constant) materials as dielectrics is a key technology. [0003] Traditional dielectric material SiO 2 It has...

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Problems solved by technology

[0005] However, when ultra-low-k material layers are etched, for example, by dry etching using plasma, the hydrophobicity of these materials may be compromised

[0006] Especially for a porous ultra-low-k material layer with a large specific surface area, the decline in hydrophobicity will lead to the absorption of water in its pores, which will cause a shift in the k value and seriously affect the device performance.

For example, it is sometimes observed that the k value of porous carbon-doped silicon oxide film (SiOCH) drifts from 2.59 to 2.91, an increase of nearly 12%, which seriously reduces the reliability of the device

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