A sonar hardware-in-the-loop simulation system

Abstract

The invention discloses a sonar semi-physical simulation system which comprises a simulation upper computer, a D / A (digital-to-analog) change-over box, a signal acquisition module, a bus back plate, a DSP (digital signal processing) board and a signal processing upper computer, wherein the DSP board and the signal processing upper computer form a signal processing operation part. The tree topology semi-physical simulation system can verify correctness, instantaneity and effectiveness of a tree structure algorithm, and is fine in universality.

Description

technical field [0001] The invention relates to mathematical simulation technology, in particular to the simulation technology in sonar signal processing. Background technique [0002] The design of large-scale digital signal processing systems generally goes through the design stages of pure software simulation, hardware-in-the-loop simulation, and equipment prototype, among which hardware-in-the-loop simulation is a key step for the algorithm to be transplanted from software simulation to hardware. The hardware-in-the-loop simulation system software design is based on the hardware structure of the corresponding system, and can only verify the validity and real-time properties of the algorithm under the corresponding hardware architecture. [0003] The processor hardware of a typical sonar system uses a cascaded topology such as figure 1 As shown in the figure, this structure is completed by multi-chip processors in cooperation, and the communication between each chip proc...

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Problems solved by technology

[0006] 1) Typical sonar hardware-in-the-loop simulation system software design and implementation methods are only suitable for cascaded system structures, which cannot meet the requirements of the tree topology signal processing system developed in this laboratory

[0007] 2) The hardware-in-the-loop simulation platform software based on the cascade structure cannot verify the correctness, real-time performance, and effectiveness of the algorithm under the tree structure

[0008] 3) The hardware-in-the-loop platform software based on the cascade structure has poor real-time performance and low simulation efficiency

When using the shared memory method for transfer, it is obviously limited by the read and write speed of the memory

[0009] 4) Since the two-level processing units share the same data area of ​​the external memory during communication, it is necessary to synchronize the two-level processors to prevent errors in simultaneous read and write operations. The hardware-in-the-loop platform software control based on the cascade structure is complex and difficult to design

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