Look-up tables for delay circuitry in field programmable gate array (fpga) chipsets

Abstract

A method, new use for Look-Up Tables (LUTs), and a Field Programmable Gate Array (FPGA) chipset are provided for delaying data signals. The FPGA comprises an input and a set of LUTs operationally connected to and receiving from the interface a data signal and a clock signal. The set of LUTs delay the data signal by a delay so that a corresponding first delayed data signal output from the set of LUTs is so synchronized with the clock signal for appropriate sampling of the delayed data signal to be performed by the FPGA chipset. A process of manufacturing of the FPGA chipset comprises calculating a delay for delaying and synchronising the data signal with a clock signal to meet requirements of the chipset, calculating a number of LUTs for delaying the data signal, and implementing in a data path of the data signal the number of LUTs.

Description

technical field [0001] The present invention relates to the field of Field Programmable Gate Array (FPGA) chipsets. Background technique [0002] A Field Programmable Gate Array (FPGA) is an integrated circuit designed to be configured by a customer or designer after manufacture. The FPGA configuration can be specified using a hardware description language (HDL), similar to the language used for application specific integrated circuits (ASICs). An FPGA can be used to implement any logic function that an ASIC can perform. The ability to update functionality after shipment, partial reconfiguration of parts of the design, and low incidental engineering costs relative to ASIC design (albeit generally higher unit costs) offer advantages for many applications. An FPGA contains programmable logic components called "logic blocks" and a hierarchy of reconfigurable interconnects that allow blocks to be "wired together", sort of like a reconfigurable interconnection of many (changeab...

AI Technical Summary

Problems solved by technology

In many designs, this clock speed is not needed without delay cells, and so such implementations often make FPGA cells more expensive

Images