Simulation testing system of non-volatile memory (NVM) built-in self-testing circuit

Abstract

The invention discloses a simulation testing system of a non-volatile memory (NVM) built-in self-testing circuit. The simulation testing system of the NVM built-in self-testing circuit comprises a testing host computer, a plurality of simulation modules, an NVM chip circuit, the NVM built-in self-testing circuit, and an automatic detection module. The automatic detection module specifically comprises an interface signal detecting module, a system state detecting module, an instruction execution timing sequence detecting module, a test integrity detecting module, a data output module, and a test vector output module. According to the simulation testing system of the NVM built-in self test circuit, workload of detection of the NVM built-in self-testing circuit is greatly reduced, and integrity of a test is guaranteed.

Description

technical field [0001] The invention relates to a simulation test system of NVM (Non-Volatile Memory, non-volatile memory). Background technique [0002] The built-in self-test (Built-in Self Test, referred to as BIST) technology is to implant a circuit that provides a self-test function into the circuit design, so as to reduce the dependence of device testing on automatic test equipment (ATE). BIST technology can be applied to almost all circuits, so it is widely used in the semiconductor industry. [0003] For example, the BIST technology commonly used in NVM includes implanting test pattern generation circuits, sequential circuits, mode selection circuits, and debugging test circuits in NVM circuits, which are collectively referred to as BIST circuits. [0004] see figure 1 , which is an existing NVM BIST circuit simulation test system. The system includes a test host 1 ; a plurality of analog modules 21 , 22 , 23 , . . . ; an NVM chip circuit 31 ; and a BIST circuit 3...

AI Technical Summary

Problems solved by technology

The third is difficult to debug

The fourth is that it cannot provide test vectors for silicon wafer test machines

The fifth is that the integrity of the test vector cannot be automatically detected

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