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High-efficiency system based on central processing unit (CPU)/many integrated core (MIC) heterogeneous system structure

An architecture and high-efficiency technology, applied in the field of high-performance computing, to solve performance bottlenecks and power consumption problems, reduce construction costs and management, and low power consumption

Inactive Publication Date: 2013-04-17
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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AI Technical Summary

Problems solved by technology

[0004] Computing speed is particularly important for high-performance computing. High-performance computing will develop towards multi-core and many-core, and use heterogeneous parallelism to improve application computing speed. Currently, CPU+GPU is a very mature heterogeneous collaborative computing model. There are huge challenges in fine-grained parallel algorithms and large-scale parallel performance

Method used

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  • High-efficiency system based on central processing unit (CPU)/many integrated core (MIC) heterogeneous system structure

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Embodiment

[0046] The technical characteristics and advantages of the high-efficiency system will be described in detail below through an embodiment. The high-efficiency system in this embodiment is designed as follows.

[0047] (1) Hardware part design

[0048] a) Each node of the system adopts dual channels and supports two CPUs to work at the same time. In this implementation process, the system uses two intel Xeon56756 core CPUs with a main frequency of 3.07GHz;

[0049] b) The system has more than two PCIE slots, which can insert 2 MIC cards. This system uses 2 MIC cards, and each card has 30 cores;

[0050] c) The memory configuration of the system should be large, and each node of this system is equipped with 96GB of memory;

[0051] d) The power consumption of each node of the system supports more than 1300w to ensure the normal operation of the whole system. The maximum power of this system supports 1300w.

[0052] (2) System environment configuration

[0053] a) The operati...

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Abstract

The invention provides a high-efficiency system based on a CPU / MIC heterogeneous system structure, and relates to the field of high-performance computing of computers. The whole system design comprises hardware portion design, system environment configuration and software portion design. The system achieves software and hardware integrated design, the CPU / MIC heterogeneous system structure is utilized, the system integrates the multi-core computing capacity of the CPU platform with the many-core computing capacity of the MIC, wherein the CPU participates in logic computing and intensive core computing, the MIC only participates in intensive core computing, and the performance is maximized through common computing of the CPU and the MIC. The high-efficiency system has the advantages that the system solves the problems of the performance bottleneck and power consumption of high-performance computing applications through the cooperative computing of the CPU and the MIC and has the advantages of being high in performance and low in power consumption, and the computer room construction cost and management, operation and maintenance costs are reduced.

Description

technical field [0001] The present invention relates to the field of high-performance computing, specifically a CPU / MIC heterogeneous architecture-based [0002] High performance system. Background technique [0003] High-performance computing is a cutting-edge high-tech in the field of information. With the rapid development of the information society, human beings have higher and higher requirements for information processing capabilities. Not only oil exploration, weather forecast, aerospace defense, scientific research, etc. require high-performance computing, The demand for high-performance computing in wider fields such as finance, government informatization, education, enterprises, and online games is growing rapidly. [0004] Computing speed is particularly important for high-performance computing. High-performance computing will develop towards multi-core and many-core, and use heterogeneous parallelism to improve application computing speed. Currently, CPU+GPU is ...

Claims

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Application Information

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IPC IPC(8): G06F9/50G06F9/38
CPCY02D10/00
Inventor 张清张广勇
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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