Self-adaption timing sequence calibrating method of high-speed serial communication interface

Abstract

A self-adaption timing sequence calibrating method of a high-speed serial communication interface is achieved by adoption of the Field Programmable Gate Array (FPGA). The method comprises the steps of setting the high-speed serial communication interface as a calibrating mode; converting serial data received by the high-speed serial communication interface to parallel data; adjusting the sampling clock phase or sampling time delay to obtain an optimal sampling point; configuring the high-speed serial communication interface by using the optimal sampling point; converting the serial data received by the high-speed serial communication interface to the parallel data again; comparing the obtained parallel data with a preset value and adjusting the parallel data latching moment according to a comparison result to enable the parallel data received by the high-speed serial communication interface to coincide with the preset value; configuring the high-speed serial communication interface by using an obtained data latching moment result; and setting the high-speed serial communication interface as a transmission mode. The self-adaption timing sequence calibrating method of the high-speed serial communication interface is easy to achieve and power consumption is effectively reduced.

Description

technical field [0001] The invention relates to a logic circuit design, in particular to a high-speed serial communication interface adaptive timing calibration method, which is suitable for timing calibration of the high-speed serial communication interface. Background technique [0002] The rendezvous and docking task has higher requirements on the pixel and image processing efficiency of optical sensitive equipment, so a higher speed serial bus is required to download the image data to the processing unit for calculation. Due to space-borne applications, it is not yet possible to obtain dedicated aerospace-grade image transceiver chips in China, so FPGA chips with radiation resistance are generally used as image transceiver and processing units. The high-speed serial bus is divided into one common clock, one control signal, and several data transmission channels. If the FPGA adopts the conventional full-synchronous design method, according to Shannon’s sampling law, the ...

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Problems solved by technology

However, since each pixel data does not have a related synchronization signal, how to confirm the start and end of each pixel data bit in a data sequence and latch it to ensure that the serial data is received correctly is also a key issue that needs to be solved

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