Word line biasing circuit and storage

Abstract

A word line biasing circuit includes a voltage detection unit for outputting control signals, a drive unit for outputting low voltage drive signals, a first state control unit, a first level shifting unit for outputting high voltage drive signals, a second state control unit, a comparison unit, and a second level shifting unit, wherein the first state control unit is driven by the low voltage drive signal to output power voltage to a second biasing voltage output end in case that a first enable signal is effective; the second state control unit is driven by the high voltage drive signal to output target voltage to a second biasing voltage output end in case that a second enable signal is effective; the comparison unit is suitable for comparing the voltage of the second biasing voltage output end and the reference voltage and outputting comparison results; and the second level shifting unit is suitable for outputting the first enable signal and the second enable signal as per the comparison results. The word line biasing circuit provided by the technical scheme of the invention can reduce GIDL current when erasure operation is performed to a storage unit, and cannot cause extra power consumption.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a word line bias circuit and memory. Background technique [0002] The storage unit of the memory (for example, flash memory Flash Memory) usually includes four leads: bit line (BL, Bit-Line), word line (WL, Word-Line), source line (SL, Source-Line) and baseline (SBL, Sub-Line), which are respectively coupled to the drain, gate, source and base of the MOS transistor. Generally, when performing an erase operation on a memory cell of a memory, a high voltage needs to be applied to a word line. [0003] figure 1 A schematic diagram of a circuit structure of a memory cell array and a word line decoding circuit in a memory in the prior art is shown. refer to figure 1 As shown, the memory cell array 13 in the memory is composed of NMOS transistors, the gates of the memory cells A0, A1, ..., Ak shown are all connected to the word line WL, and the drains are respectively connected to ...

AI Technical Summary

Problems solved by technology

The second bias voltage Vb2 in the prior art is usually provided by a power supply voltage, image 3 Shown is a timing diagram of the stable high voltage VEP and the second bias voltage Vb2. If the voltage detection unit 24 is missing, the stable high voltage VEP and the second bias voltage Vb2 will rise simultaneously, and the first bias voltage Vb1 may be lower than the first bias voltage Vb1. The second bias voltage Vb2 causes the logic confusion of the memory cell erasing operation

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