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Super-junction device and manufacturing method thereof

A manufacturing method and super junction technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problem that the breakdown voltage is prone to large changes, the reverse breakdown voltage of the device has a large variation range, and the trench Depth is prone to change and other issues

Active Publication Date: 2013-03-27
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The other is to etch the trench after growing one type of epitaxy with the required thickness at a time, and then fill the trench with silicon of the opposite type; the process cost and process cycle of this method are short; but if the thin layer There is a certain thickness between the groove and the substrate. Due to certain process changes in the etching of the groove, the depth of the groove is easy to change, so the reverse breakdown voltage of the device varies widely.
Especially when the distance between the bottom of the trench and the N+ substrate is less than a certain value, not only the breakdown voltage of the device tends to change greatly with the change of the process, but also the anti-current impact capability of the device such as the single pulse avalanche breakdown energy (FAS) also undergoes large changes, which greatly affects the consistency of the device

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  • Super-junction device and manufacturing method thereof
  • Super-junction device and manufacturing method thereof
  • Super-junction device and manufacturing method thereof

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Embodiment Construction

[0070] Such as figure 1 Shown is the top view of the super junction device of the embodiment of the present invention Figure 1 . In the top view, the embodiment of the present invention can be divided into zone 1, zone 2 and zone 3. Region 1 is the middle region of the super junction device, which is the current flow region, and the current flow region includes alternately arranged P-type regions 25 and N-type regions formed in the N-type silicon epitaxial layer 2, and the P-type regions 25 are also The P-type thin layer formed in the current flow region, the N-type region is also the N-type thin layer formed in the current flow region; in the current flow region, the current will pass through the N-type region from the source It reaches the drain through the channel, and the P-type region 25 is in the reverse cut-off state and forms a depletion region together with the N-type region to withstand the voltage. Regions 2 and 3 are the terminal protection structure regions of t...

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Abstract

The invention discloses a super-junction device. All P-type thin layers in a current flow region do not contact with an N+ silicon substrate. The distances from the bottoms of all the P-type thin layers in the current flow region to the surface of the N+ silicon substrate are larger than the thickness of a transition region between an N-type silicon epitaxial layer and the N+ silicon substrate. The invention further discloses a manufacturing method of the super-junction device. Consistence between reverse breakdown voltage and overshoot current resistance of the super-junction device can be improved, and accordingly the reverse breakdown voltage and overshoot current resistance of the super-junction device can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a super junction device; the invention also relates to a manufacturing method of the super junction device. Background technique [0002] The super junction MOSFET adopts a new voltage-resistant layer structure, and uses a series of alternately arranged P-type semiconductor thin layers and N-type semiconductor thin layers to combine the P-type semiconductor thin layers and N-type semiconductor thin layers at a lower voltage in the off state. The thin layer of semiconductor is depleted to achieve mutual compensation of charges, so that the thin layer of P-type semiconductor and thin layer of N-type semiconductor can achieve high breakdown voltage under high doping concentration, so as to obtain low on-resistance and high breakdown at the same time voltage, breaking the theoretical limit of traditional power MOSFETs. In U.S. Patent US5216275, the above...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/78H01L21/336
CPCH01L29/0878H01L29/78H01L29/66712H01L29/1095H01L29/404H01L29/0619H01L21/20H01L29/0696H01L29/7811H01L29/0638H01L29/0634
Inventor 肖胜安
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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