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Methods and systems for digital neural processing with discrete-level synapses and probabilistic stdp

A synapse and nerve technology, applied in the field of nervous system engineering, which can solve the problems of large die area, poor retention and cloning ability of analog memory, and large bits of multi-level digital memory.

Inactive Publication Date: 2013-03-06
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Analog memory has poor retention and cloning capabilities
It also requires a large die area for STDP attenuation
On the other hand, multi-level digital memory requires a large number of bits, which results in a large number of parallel interconnect lines in order to achieve a given precision of synaptic weight increments

Method used

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  • Methods and systems for digital neural processing with discrete-level synapses and probabilistic stdp
  • Methods and systems for digital neural processing with discrete-level synapses and probabilistic stdp
  • Methods and systems for digital neural processing with discrete-level synapses and probabilistic stdp

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Embodiment Construction

[0020] Various embodiments of the invention are described more fully hereinafter with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function set forth throughout this disclosure. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Based on the teachings herein, one skilled in the art should appreciate that the scope of the present invention is intended to cover any embodiment of the invention disclosed herein, whether implemented independently of or implemented in conjunction with any other embodiments of the invention. realized in combination. For example, an apparatus may be implemented or a method may be implemented using any number of the embodiments set forth herein. Furthermore, the scope of the present invention is intended t...

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Abstract

Certain embodiments of the present disclosure support implementation of a digital neural processor with discrete-level synapses and probabilistic synapse weight training.

Description

technical field [0001] Certain embodiments of the invention relate generally to neural systems engineering, and more specifically, to a method for implementing a digital neural processor with discrete-level synapses and probabilistic synaptic weight training. Background technique [0002] Synapses connecting neurons of the nervous system typically exhibit only a small number of discrete intensity levels. For example, synapses in the CA3-CA1 channel of the Cornu Ammonis (Cornus Ammonis) in the hippocampal neural structure can be dimorphic or trimorphic. For example, in the case of tri-state synapses, one intensity level may correspond to an inhibitory state caused by long-term depression (LTD), and another intensity level may correspond to a potentiated state caused by long-term potentiation (LTP), And the third intensity level may correspond to the unstimulated state that existed prior to application of LTP or LTD. Switching between discrete levels of synaptic strength can...

Claims

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Application Information

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IPC IPC(8): G06N3/063G06N3/04
CPCG06N3/049G06N3/063G06N3/0472G06N3/088G06N3/047
Inventor V·阿帕林S·文卡特拉曼
Owner QUALCOMM INC
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