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Design method for field programmable analog array (FPAA)-based reconfigurable vector-matrix multiplier

A technology of a matrix multiplier and a design method, which is applied in the calculation using the number system, the calculation using the non-contact manufacturing equipment, and the complex mathematical operation, etc. question

Inactive Publication Date: 2013-02-13
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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Problems solved by technology

[0004] The purpose of the present invention is to solve the problem that the existing analog vector-matrix multiplication integrated circuit generally cannot adjust the matrix coefficients online and the operation scale is fixed, and proposes a design method for analog reconfigurable vector-matrix multipliers, and constructs a method based on A new type of FPAA based on transconductance operational amplifiers and floating gate transistors, and a reconfigurable analog vector-matrix multiplier based on FPAA is designed to realize variable operation scale and adjustable coefficients of the analog vector-matrix multiplier

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  • Design method for field programmable analog array (FPAA)-based reconfigurable vector-matrix multiplier
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  • Design method for field programmable analog array (FPAA)-based reconfigurable vector-matrix multiplier

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Embodiment Construction

[0017] Below in conjunction with accompanying drawing, the patent of the present invention is described in further detail.

[0018] The mathematical expression of the vector-matrix multiplier is:

[0019] y i = Σ j = 1 n w ij x j , i=1,K,m.

[0020] Among them, w ij is the matrix of multiplicative coefficients, x j is the input vector, y i is the output vector. n is the number of elements in the input vector (corresponding to the number of multiplier input signals), and m is the number of elements in the output vector (corresponding to the number of multiplier output signals). The vector-matrix multiplier operation is actually a multiply-accumulate process.

[0021] figure 1 It is a 2×2 (m=n=2) analog vector-matrix multiplier circuit, the input vect...

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Abstract

The invention discloses a design method for a field programmable analog array (FPAA)-based reconfigurable vector-matrix multiplier. According to the method, a novel FPAA based on a transconductance operational amplifier and a floating gate transistor is designed, then an analog vector-matrix multiplier principle circuit is designed, and a design process of adopting SIMULINK, Sim2Spice, GRASPER and RAT software tools to realize the reconfigurable analog vector-matrix multiplier is proposed. The configurable analog vector-matrix multiplier designed by the method can realize a variable operation scale and an adjustable matrix coefficient.

Description

technical field [0001] The invention relates to a vector-matrix multiplier design technology, in particular to a reconfigurable vector-matrix multiplier VMM (Vector-Matrix Multiplier) design method. Background technique [0002] Vector-matrix multiplication is widely used in signal processing, image processing, radar, sonar, communication and other complex computing fields, and can realize functions such as FIR digital filtering, image transformation, time-frequency analysis, convolution and correlation calculation. Vector-matrix multiplication operations can be implemented using general-purpose processors and dedicated hardware. Using a general-purpose processor (such as a digital signal processor DSP) to perform vector-matrix multiplication through software requires high processor requirements and high power consumption; using an application-specific integrated circuit to realize vector-matrix multiplication has high integration, fast speed, The advantage of low power con...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/16G06F7/52
Inventor 王友仁任晋华陈燕
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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