Successive Approximation Analog-to-Digital Converter

Abstract

The invention discloses a successive approximation type analog / digital converter, wherein a capacitor array digital / analog conversion circuit comprises a capacitor array, an auxiliary capacitor is connected between the capacitor array and the output end of a comparer, and the oscillation amplitude between the capacitor array and the output end of the comparer ranges from 0V to power voltage when the capacitance value of the auxiliary capacitor is selected in a range enabling the oscillation amplitude of the input voltage to be from 0V to the power voltage. A measure of carrying out limiting and compression on a quantification range or increasing complicated circuits, which is adopted for preventing voltage overshoot in the traditional scheme, is avoided. According to the circuit structure provided by the invention, the requirements on input offset of the comparer in the ADC (analog / digital converter) and performance of other internal circuits are reduced, so that higher resolution ratio can be achieved under the condition of not increasing power consumption of the ADC using the circuit structure.

Description

technical field [0001] The invention relates to the design of a CMOS integrated circuit, in particular to a high-precision successive approximation analog-to-digital converter suitable for standard CMOS technology. Background technique [0002] The successive approximation ADC circuit with capacitor array DAC uses the principle of charge calibration to complete the analog-to-digital conversion process. The charge calibration method uses the capacitor array to transfer and redistribute the charge, sets the comparison voltage of the comparator, and judges successively to obtain the analog-to-digital conversion result. This type of SARADC circuit structure is simple, most of the work is done by the control circuit control switch, and the power consumption is the lowest among various SARADC circuit structures, so it is embedded in a large number of chips realized by standard CMOS technology, as a chip implementation and off-chip simulation Interface circuit for analog-to-digita...

AI Technical Summary

Problems solved by technology

However, this solution loses the resistance of the differential circuit to common-mode interference, and also turns the Sc switch that can be formed with a single MOS transistor into a complex bootstrap switch, which is uneconomical in terms of power consumption and layout area.

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