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Bang-bang discriminator used for half speed rate clock data restoring circuit

A clock data recovery and half-rate technology, which is applied in the field of phase detectors, can solve the problems of voltage-controlled oscillator control voltage fluctuations and deterioration of system clock jitter indicators, etc., to achieve the effect of reducing glitches, eliminating wrong pairing, and satisfying high-speed systems

Inactive Publication Date: 2012-11-28
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

Its transient effect will also cause fluctuations in the control voltage of the voltage-controlled oscillator, deteriorating the clock jitter index of the system

Method used

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  • Bang-bang discriminator used for half speed rate clock data restoring circuit
  • Bang-bang discriminator used for half speed rate clock data restoring circuit
  • Bang-bang discriminator used for half speed rate clock data restoring circuit

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Experimental program
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Embodiment Construction

[0019] The circuit diagram of the half rate bang-bang phase detector of the present invention is as image 3 shown. The sampling circuit trigger module includes 4 D flip-flops 301, 302, 303, 304, the resynchronization trigger module includes 4 D flip-flops 311, 312, 313, 314, and the decision module includes 4 XOR gates 321, 322, 323, 324, the double-edge trigger module includes two double-edge triggers 331, 332;

[0020] The data input ends of the four D flip-flops in the sampling circuit trigger module receive the original data, and the clock input ends of the four D flip-flops 301, 302, 303, and 304 are respectively connected to clock pulses clk0, clk90, clk180, and clk270; connected to clock pulses clk0 The output end of the D flip-flop 301 is connected with the data input end of the D flip-flop 311 in the resynchronization trigger module and an input end of the XOR gate 324 in the decision module respectively; the output end of the D flip-flop 303 connected with the cloc...

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Abstract

The invention provides a bang-bang discriminator used for a half speed rate clock data restoring circuit, which can generate exact paired judging indication signal. The bang-bang discriminator comprises a sampling circuit trigger module, a judging module, a two-edge trigger module and a resynchronization trigger module. According to the invention, a first-level resynchronization trigger module is additionally arranged between the sampling circuit trigger module and the judging module; the output of the resynchronization trigger module is matched with the output of the sampling circuit trigger module so as to connect the input of a rear level circuit, so that the judging comparative signal every time is output at the same time and is effective; and the generating inaccuracy paired condition is basically eliminated, and the fluctuation of the control voltage of the oscillator is avoided.

Description

technical field [0001] The present invention relates to phase detector technology. Background technique [0002] In high-speed data communications, data streams are typically transmitted over high-speed serial interfaces. In the high-speed serial interface, the system often only transmits the data signal, but does not transmit the clock signal at the same time. Therefore, at the receiving end, the system needs to recover the clock information from the data signal, and use the recovered clock signal to complete all subsequent systems. This is the basic function of the Clock and Data Recovery (CDR) circuit. As the speed of data flow continues to increase, for example, when it is higher than 10Gbit / s, it is difficult for the receiving end to design a voltage-controlled oscillator (Voltage Control Oscillator, VCO) that generates such a high-frequency signal and meets the stringent clock jitter index at the same time. Therefore, the half-rate clock data recovery circuit can wel...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/08
Inventor 张军娄佳宁高园林易勇军郑侃刘辉华李磊周婉婷
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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