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Idle state test method of system-on-chip (SoC), system and test device

An idle state and test method technology, applied in the embedded field, can solve problems such as increased data processing by the test system, continuous testing of multiple test cases, and reduced test efficiency of the test system, achieving the effect of improving test efficiency and reducing processing capacity

Active Publication Date: 2012-10-17
ANYKA (GUANGZHOU) MICROELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the embodiments of the present invention is to provide a SoC chip idle state testing method, system and testing device, aiming to solve the problem that the existing testing method cannot carry out continuous testing of multiple test cases, resulting in an increase in the processing data of the testing system. The problem of reduced test efficiency

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Embodiment 1

[0037] In the embodiment of the present invention, all test cases that SoC chips enter / exit idle state are stored in random access storage, and the one-to-one correspondence between the identification number and all test cases is established, and the test cases are executed in the SoC chip startup process. , until all the test cases of all SoC chips entering / exiting the idle state are tested.

[0038] figure 1 The implementation flow of the idle state test method of the SoC chip provided by the first embodiment of the present invention is shown, and the details are as follows:

[0039] In step S101 , the power-on reset of the SoC chip is performed. After the power-on reset of the SoC chip, an identification number is obtained from a preset location in a preset random access memory.

[0040]SoC chip is a system-level chip with certain functions, which can include control logic module, microprocessor / microcontroller CPU core module, digital signal processor DSP module, embedded...

Embodiment 2

[0050] figure 2 The implementation process of the idle state test method of the SoC chip provided by the second embodiment of the present invention is shown, and the details are as follows:

[0051] In step S201, the test case to be tested is compiled, and the compiled test case is saved to a preset random access memory.

[0052] In the embodiment of the present invention, the test case to be tested is compiled in advance, and the compiled test case is saved to a preset random access memory, thereby improving the test efficiency of the test system.

[0053] In step S202, establish and store the correspondence between the identification number of the test case and the test case.

[0054] In step S203, the power-on reset of the SoC chip is performed. After the power-on reset of the SoC chip, an identification number is obtained from a preset location in a preset random access memory.

[0055] SoC chip is a system-level chip with certain functions, which can include control lo...

Embodiment 3

[0064] image 3 The structure of the idle state testing system of the SoC chip provided by the third embodiment of the present invention is shown, and for the convenience of description, only the parts related to the embodiment of the present invention are shown.

[0065] The idle state test system of this SoC chip can be used in the test platform of the idle state function of testing SoC chip, or in the SoC test device with the idle state test of SoC chip, can be the software unit that runs in these SoC test devices, It can also be integrated into these SoC test devices as an independent pendant or run in the application systems of these SoC test devices, wherein:

[0066] The test case compiling unit 31 compiles the test case to be tested, and saves the compiled test case to a preset random access memory.

[0067] In the embodiment of the present invention, the test case to be tested is compiled in advance, and the compiled test case is saved to a preset random access memor...

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Abstract

The invention is suitable for the embedded technology field and provides an idle state test method of a system-on-chip (SoC), a system and a test device. The method comprises the followings steps: A. Carrying out power-on reset of the SoC and acquiring an identification number from a preset position in a preset random access memory; B. Calculating the identification number of a test case, wherein the test case is the test case of entering into / exiting the idle state of the SoC; C. Determining whether the identification number of the test case is a null character, if the identification number of the test case is the null character, exiting the test of the SoC, and if the identification number of the test case is not the null character, acquiring an address of the test case and executing the test case; after the test is completed, writing the identification number of the test case into the preset position of the preset random access memory and entering into the step A. According to the invention, batch test of the test case of entering into / exiting the idle state of the SoC is realized; test efficiency of a test system is increased and a processing amount of data is reduced.

Description

technical field [0001] The invention belongs to the field of embedded technology, and in particular relates to an idle state testing method, system and testing device of a SoC chip. Background technique [0002] A system-on-chip (SoC, System-on-Chip) is an integrated circuit with a dedicated target, which can be a complete system, such as a microprocessor ARM, an intellectual property core (IP core) and a memory. At the same time, SoC chip is also a general term for a technology, which is used to realize the whole process from determining the system function, to software / hardware division, and to complete the design. [0003] At present, SoC chips have been widely used in various handheld devices, such as digital cameras, smart phones, etc., which requires SoC chips to have low power consumption. In order to reduce the power consumption of SoC chips, more effective methods It is to turn off the power of the temporarily unused modules in the SoC chip, so that the SoC chip en...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
Inventor 王恒军胡胜发
Owner ANYKA (GUANGZHOU) MICROELECTRONICS TECH CO LTD
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