Memory controller and a controlling method adaptable to dram

Abstract

A memory controller and controlling method adaptable to a dynamic random access memory (DRAM) are disclosed. A DRAM controller is configured to manage flow of data to and from the DRAM. A write buffer is controlled by the DRAM controller to temporarily store an entry of data to be written to the DRAM. The data to be written is stored in the write buffer if the write buffer is empty, and the stored data and a succeeding data to be written are both written to the DRAM.

Description

technical field [0001] The invention relates to a memory controller, in particular to a dynamic random access memory (DRAM) memory controller. Background technique [0002] Dynamic Random Access Memory (DRAM) is a type of volatile memory that stores each data bit in a separate capacitor. DRAM comes in various types, such as Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), DDR2 SDRAM, and DDR3 SDRAM, each with different densities and operating speeds. [0003] A memory controller, such as a DRAM controller, is a circuit that manages the flow of data to and from memory such as DRAM. The memory controller controls reading and writing by selecting the column and row addresses of the memory. [0004] In addition to a memory controller, today's memory is also equipped with a cache mechanism for storing data in a cache, such as static random access memory (SRAM). If the requested data is located in the cache (called a hit), it can be quickly read from the cache, the...

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Problems solved by technology

[0007] This shows that the above-mentioned existing memory controller obviously still has inconvenience and defects in method, product structure and use, and needs to be further improved urgently

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