Configuration method for strobe enabling opportunity of read operation data of memory

Abstract

The invention discloses a configuration method for strobe enabling opportunity of read operation data of a memory. The configuration method mainly comprises the following steps of: selecting a certain data set, performing maximum value training and minimum value training of a read strobe enabling register, and acquiring the maximum value and the minimum value which can be configured by the read strobe enabling register; solving an arithmetic mean value of the two acquired values, and taking the arithmetic mean value as a read strobe enabling register final value required to be configured; and performing formula conversion, and acquiring the final value of a read strobe enabling coarse adjustment register, wherein the final value is equal to the arithmetic mean value of the coarse adjustment value corresponding to the maximum value of the read strobe enabling register and the coarse adjustment value corresponding to the minimum value; and the final value of the read strobe enabling coarse adjustment register is equal to the arithmetic mean value of the coarse adjustment value corresponding to the maximum value of the read strobe enabling register and the coarse adjustment value corresponding to the minimum value. According to the configuration method, the phenomenon that the minimum unit value of the read strobe enabling coarse adjustment register is known is prevented, and the strobe enabling opportunity of the read operation data is configured under the condition that the minimum unit of the read strobe enabling coarse adjustment register is unknown.

Description

technical field [0001] The invention relates to a method for configuring the enable timing of the memory controller read operation data gate, which belongs to the field of computer memory controllers. Background technique [0002] In the double data rate 3 (DDR3) memory controller, on the memory module, the clock signal, address signal, command signal, and control signal adopt the Fly-By Bus (Fly-By Bus) routing method. In the memory read operation, after the memory controller sends out the read command, the read command will pass through each memory chip on the memory channel one by one along with the flying bus, and then these memory chips will send out data after receiving the read command at the same time interval. The strobe signal (DQS) is transmitted to the memory controller, so the data strobe signals from different memory chips on the same memory channel will reach the memory controller at different times. [0003] The fly-by bus on the same memory channel passes t...

AI Technical Summary

Problems solved by technology

[0006] However, the relevant documents of some DDR3 memory controllers do not specify the size of the smallest unit of the read strobe enable trimming register, only that it is a fixed time length value and has nothing to do with the clock cycle

Therefore, when the specific size of the minimum unit of the read strobe enable coarse adjustment register is clear, but the minimum unit of the read strobe enable fine adjustment register is not clear, the configuration of the final value of the read strobe enable register becomes a difficult problem

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