A kind of semiconductor structure and its manufacturing method

Abstract

The invention provides a method for manufacturing a semiconductor structure, comprising the following steps: providing a semiconductor substrate, and forming an epitaxial layer on the semiconductor substrate; forming a semiconductor device on the epitaxial layer; forming a leakage current absorption region, the The leakage current absorbing region is located at one side of the drain region of the semiconductor device and is not in contact with the drain region. Correspondingly, the present invention also provides a semiconductor structure manufactured by applying the method. The method and the semiconductor structure of the invention can effectively reduce the leakage current in the thick epitaxial device, and further improve the overall performance of the semiconductor device.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] Static electricity exists all the time in nature. When the human body can feel the existence of static electricity, the static electricity generated has reached tens of thousands of volts, which is enough to damage most electronic components. [0003] With the development of the semiconductor industry, integrated circuits with higher performance and stronger functions require greater component density, and the size, size, and space of each component, between components, or each component itself need to be further reduced (currently, it has reached nanometers. level), so the requirements for process control in the manufacturing process of semiconductor devices are relatively high. [0004] However, when the external environment of the chip or the static charge accumulated inside ...

AI Technical Summary

Problems solved by technology

Applying this method can effectively solve the problem of excessive leakage current due to the amplification effect of parasitic BJT when using NMOS / PMOS or CascadedNMOS / PMOS as ESD protection in thick epitaxial devices

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