Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a method for manufacturing a semiconductor structure. The method comprises the following steps of: providing a semiconductor substrate and forming an epitaxial layer on the semiconductor substrate; forming a semiconductor device on the epitaxial layer; forming a leakage current absorbing region, wherein the leakage current absorbing region is located at one side of a leakage region of the semiconductor device and does not contact with the leakage region. Accordingly, the invention further provides a semiconductor structure manufactured by the method. With the adoption of the method and the semiconductor structure disclosed by the invention, the leakage current in a thick epitaxial device can be effectively reduced, and thus the whole performance of the semiconductor device can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] Static electricity exists all the time in nature. When the human body can feel the existence of static electricity, the static electricity generated has reached tens of thousands of volts, which is enough to damage most electronic components. [0003] With the development of the semiconductor industry, integrated circuits with higher performance and stronger functions require greater component density, and the size, size, and space of each component, between components, or each component itself need to be further reduced (currently, it has reached nanometers. level), so the requirements for process control in the manufacturing process of semiconductor devices are relatively high. [0004] However, when the external environment of the chip or the static charge accumulated inside ...

AI Technical Summary

Problems solved by technology

Applying this method can effectively solve the problem of excessive leakage current due to the amplification effect of parasitic BJT when using NMOS / PMOS or Cascaded NMOS / PMOS as ESD protection in thick epitaxial devices

Images