Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Manufacturing method of semiconductor device

A manufacturing method and semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, manufacturing tools, etc., can solve the problems of unavoidable semiconductor device manufacturing cost, increase, design constraints, etc., and achieve the suppression of voids and poor connections. Effect

Inactive Publication Date: 2012-07-18
TOSHIBA MEMORY CORP
View PDF6 Cites 6 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this method, since the steps from removal of the oxide film on the surface of the solder bump to melting of the solder bump are performed in a vacuum chamber, an increase in the manufacturing cost of the semiconductor device cannot be avoided.
In addition, since the conventional flip-chip connection cannot be used for alignment, pads made of solder are used for alignment, resulting in cost increases and design restrictions.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Manufacturing method of semiconductor device
  • Manufacturing method of semiconductor device
  • Manufacturing method of semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0026] Figure 1 ~ Figure 4 It is a figure showing the manufacturing process of the semiconductor device of 1st Embodiment. The first embodiment is a method of manufacturing a semiconductor device using flip-chip connection without using flux. Such as figure 1 As shown, a first substrate 2 having first solder bumps 1 and a second substrate 4 having second solder bumps 3 are prepared. The first substrate 2 is held, for example, by suction on the tool 5 . The second substrate 4 is arranged on a stage 6 . from figure 1 Alignment procedure shown to image 3 The temporary connection process shown is implemented using a flip-chip bonder equipped with an alignment mechanism, a heating mechanism, a height restriction mechanism, and the like.

[0027] The first substrate 2 and the second substrate 4 are, for example, semiconductor chips (silicon (Si) chips, etc.) or interposer chips (silicon (Si) interposers, etc.). The combination of the first substrate 2 and the second substra...

no. 2 Embodiment approach

[0043] Figure 6 ~ Figure 9 It is a figure which shows the manufacturing process of the semiconductor device of 2nd Embodiment. In the manufacturing process of the semiconductor device according to the second embodiment, first, the first substrate 2 having the first solder bumps 1 and the second substrate having the second solder bumps 3 are prepared in the same manner as in the first embodiment. 4, such as Image 6 As shown, the first solder bump 1 and the second solder bump 3 are aligned. Specific examples of the substrates 2 and 4 , constituent materials of the solder bumps 1 and 3 , alignment method of the solder bumps 1 and 3 , and the like are the same as those of the first embodiment. Additionally, from Image 6 Alignment procedure shown to Figure 8 The temporary connection step shown is implemented using a flip-chip bonder equipped with an alignment mechanism, a pressurization mechanism, a heating mechanism, an ultrasonic generating mechanism, and the like.

[00...

Embodiment 1

[0052] First, a first semiconductor chip on which solder bumps composed of Sn-0.7 mass % Cu are formed on electrode terminals by electroplating, and a second semiconductor chip on the connected side mounted with the first solder bumps are prepared. Solder bumps composed of Sn-0.7% by mass Cu are formed on the electrode terminals of the second semiconductor chip in the same manner as the first semiconductor chip 1 . The electrode terminals of the first semiconductor chip and the electrode terminals of the second semiconductor chip are arranged at corresponding predetermined positions so as to be connectable to each other. The number of terminals is about 2000, the height of the solder bump is 20 μm, and the minimum distance between adjacent terminals is 60 μm. No flux was used.

[0053] For these semiconductor chips, the first semiconductor chip held on the tool and the second semiconductor chip held on the stage are connected by a flip chip bonder equipped with an alignment m...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
heightaaaaaaaaaa
Login to View More

Abstract

The embodiment of the invention discloses a manufacturing method of a semiconductor device. The method comprises the following steps of: aligning and contacting a first solder bump and a second solder bump, and heating to a temperature above the melting points of the solder bumps till the solder bumps are molten to form a temporary connector for the first solder bump and the second solder bump; and heating the cooled temporary connector to a temperature above the melting points of the solder bumps in a reducing atmosphere, removing an oxide film existing on the surface of the temporary connector, and melting the temporary connector simultaneously to form a formal connector.

Description

technical field [0001] The present invention generally relates to a method of manufacturing a semiconductor device and a semiconductor device. Background technique [0002] In order to cope with the increase in the number of pins, the finer pitch of semiconductor chips, and the increase in signal speed, semiconductor devices using flip-chip connection as an assembly method with short wiring and connection lengths have been used. When flip-chip connection is used as the connection between semiconductor chips or the connection between a semiconductor chip and a silicon interposer, solder bumps are formed on the electrode terminals of the upper and lower chips (semiconductor chip or silicon interposer), respectively, After these solder bumps are laminated|stacked so that they may face each other, the solder bumps are heated and melt|dissolved, and connection is performed. [0003] In general, the following steps are used to remove the oxide film on the surface of the solder bu...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/50H01L21/60B23K1/00
CPCH01L24/75H01L24/81
Inventor 青木秀夫福田昌利泽田佳奈子小盐康弘
Owner TOSHIBA MEMORY CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com