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NoC (Network-on-Chip) multi-core processor multi-thread resource allocation processing method and system

A multi-core processor and network-on-chip technology, applied in the field of resource allocation and processing of network-on-chip multi-core processors and multi-threads, can solve the problems of occupying processor resources and wasting power consumption, and achieve the effect of improving overall performance and scalability

Active Publication Date: 2014-06-25
LOONGSON TECH CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, in the mutual exclusion control of barrier (barrier) synchronization, there is also the problem of occupying processor resources and wasting power consumption.

Method used

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  • NoC (Network-on-Chip) multi-core processor multi-thread resource allocation processing method and system
  • NoC (Network-on-Chip) multi-core processor multi-thread resource allocation processing method and system
  • NoC (Network-on-Chip) multi-core processor multi-thread resource allocation processing method and system

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Experimental program
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Embodiment approach

[0035] As an implementable manner, the operation unit includes but not limited to floating-point and integer adders, multipliers and dividers;

[0036] As an implementable manner, the Level 1 cache (L1cache) includes but not limited to an instruction cache (Instruction cache, Icache) and a data cache (Data cache, Dcache).

[0037] The resources involved in the method of accelerating the execution of the critical section and accelerating the critical thread to reach the synchronization point, as an implementable manner, may be a computing unit and a first-level cache (L1cache). Arithmetic components include floating-point and integer adders, multipliers, and dividers. Level 1 cache (L1cache) includes instruction cache (Instruction cache, Icache) and data cache (Data cache, Dcache).

[0038] By increasing the number of processor core computing components, the number of instructions transmitted from the reservation station to the functional components per beat increases, which i...

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Abstract

The invention provides a NoC (Network-on-Chip) multi-core processor multi-thread resource allocation processing method and a NoC multi-core processor multi-thread resource allocation processing system. The system comprises a detection unit, an exclusive control index table and a depriving and distributing processing unit, wherein the detection unit is used for detecting an address and a value of exclusive control in the process of executing a NoC multi-core processor multi-thread program and writing the address and the value into the exclusive control index table; the exclusive control index table is used for storing the address and the value of the exclusive control, which are detected by the detection unit; and the depriving and distributing processing unit is used for arranging threads of the exclusive control with the same address into a registration queue, depriving busy waiting core resources of part of the threads in the registration queue and distributing the busy waiting core resources to other threads for use. The integral performance and the expandability of the multi-core processor multi-thread program are effectively improved.

Description

technical field [0001] The present invention relates to the technical field of multi-thread processing on multi-core processors, in particular to a method for resource allocation and processing of multi-thread resources of a Network-on-chip (NoC) multi-core processor that dynamically changes resource allocation of multi-core processor chips and system. Background technique [0002] With the continuous application of Moore's law, more and more transistors are integrated on a single chip. In order to make full use of so many transistors to improve performance, and due to the high design complexity, power consumption and temperature limitations, The microprocessor industry has had to shift from trying to improve the performance of single-core processors with out-of-order execution to improving the performance of network-on-chip (NoC) multi-core processors. [0003] The emergence of multi-core processors, even many-core processors, makes the popularity of multi-threaded program...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/50
Inventor 尹一笑陈云霁郭崎杨旭
Owner LOONGSON TECH CORP
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