NoC (Network-on-Chip) multi-core processor multi-thread resource allocation processing method and system

A multi-core processor and network-on-chip technology, which is applied in the field of resource allocation and processing of multi-core processors and multi-threads in the network-on-chip network, can solve the problems of occupying processor resources and wasting power consumption, and achieve the effect of improving overall performance and scalability

Active Publication Date: 2012-07-18
LOONGSON TECH CORP
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Problems solved by technology

Therefore, in the mutual exclusion control of barrier (barrier) synchronization, t...

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  • NoC (Network-on-Chip) multi-core processor multi-thread resource allocation processing method and system
  • NoC (Network-on-Chip) multi-core processor multi-thread resource allocation processing method and system
  • NoC (Network-on-Chip) multi-core processor multi-thread resource allocation processing method and system

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Embodiment approach

[0039] As an implementable manner, the arithmetic components include but are not limited to floating-point and integer adders, multipliers and dividers;

[0040] As an implementation manner, the first level cache (L1 cache) includes, but is not limited to, instruction cache (Icache) and data cache (Data cache, Dcache).

[0041] The resources involved in the method of accelerating the execution of the critical region and accelerating the key thread to reach the synchronization point, as an implementable manner, may be arithmetic components and level 1 cache (L1 cache). The arithmetic components include floating-point and integer adders, multipliers and dividers. Level 1 cache (L1 cache) includes instruction cache (Icache) and data cache (Data cache, Dcache).

[0042] By increasing the number of processor core computing components, the number of instructions transmitted from the reservation station to the functional components per beat increases, which is equivalent to increasing the ...

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Abstract

The invention provides a NoC (Network-on-Chip) multi-core processor multi-thread resource allocation processing method and a NoC multi-core processor multi-thread resource allocation processing system. The system comprises a detection unit, an exclusive control index table and a depriving and distributing processing unit, wherein the detection unit is used for detecting an address and a value of exclusive control in the process of executing a NoC multi-core processor multi-thread program and writing the address and the value into the exclusive control index table; the exclusive control index table is used for storing the address and the value of the exclusive control, which are detected by the detection unit; and the depriving and distributing processing unit is used for arranging threads of the exclusive control with the same address into a registration queue, depriving busy waiting core resources of part of the threads in the registration queue and distributing the busy waiting core resources to other threads for use. The integral performance and the expandability of the multi-core processor multi-thread program are effectively improved.

Description

Technical field [0001] The invention relates to the technical field of multi-thread processing on a multi-core processor, in particular to a network-on-chip (Network-on-chip, NoC) multi-core processor multi-threaded resource allocation processing method and system. Background technique [0002] With the continuous application of Moore's law, the number of integrated transistors on a single chip is increasing. In order to make full use of so many transistors to improve performance, at the same time due to excessive design complexity, power consumption and temperature limitations, The microprocessor industry has to change from striving to improve the performance of single-core processors with out-of-order execution to improving the performance of network-on-chip (NoC) multi-core processors. [0003] The emergence of multi-core processors, and even many-core processors, makes the popularization of multi-threaded programs inevitable. Therefore, in order to improve the overall performa...

Claims

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Application Information

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IPC IPC(8): G06F9/50
Inventor 尹一笑陈云霁郭崎杨旭
Owner LOONGSON TECH CORP
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