NAND flash memory controller supporting operation out-of-order execution

Abstract

The invention discloses a NAND flash memory controller supporting operation out-of-order execution, and aims to improve memory access data throughput. The controller consists of a preprocessing module, a reservation station module, a dynamic scheduling module and a postprocessing module, wherein the preprocessing module consists of an address recognition unit, three multiplexers, a first data queue group and a first logic OR gate; the reservation station module consists of two multiplexers, a table entry number register, a validity monitoring unit, a relevance judgment unit, a substrate state setting unit, an output judgment unit, a control logic unit and a reservation station table; the dynamic scheduling module consists of five multiplexers, M state machines, an arbiter and a second logic OR gate; and the postprocessing module consists of a comparator, a second data queue group and a multiplexer. By the controller, the memory access operation of different substrates of a memory chip can be subjected to parallel execution, the working parallelism of the substrates is improved, and the memory access data throughput is effectively improved.

Description

technical field [0001] The invention relates to a storage controller of NAND flash (ie, NAND Flash) storage chip particles, in particular to a storage controller supporting out-of-order execution of operations. Background technique [0002] With the continuous development of integrated circuit technology, the volume of NAND Flash storage chip particles decreases by 40% to 50% every year, while the capacity of chip particles doubles every year. At the same time, the advancement of NAND Flash integrated circuit technology has gradually developed the internal organization structure of chip particles from traditional monomer and single substrate to multi-body and multi-substrate. For example, Micron's MT29H32G08GCAH2 memory chip has a capacity of 32Gb and contains four substrates inside. The four substrates share the I / O bus and five control signal lines: address latch signal (ALE), command latch signal (CLE), write enable signal (WE#), read enable signal (RE# ) and write-prot...

AI Technical Summary

Problems solved by technology

In the sequential structure, only a single substrate can be busy at a certain moment, and at most can only use the memory access performance of a single-substrate memory chip particle; in the decoupling structure, although multiple substrates can overlap in time , but the number of memory fetches allowed to enter the start phase is still limited

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