Testing device and method for digital semiconductor device

Abstract

The invention discloses a testing device and method for a digital semiconductor device; the testing device comprises a time series generator module, an algorithm vector generator module, a programmable data selector module and a testing module, wherein the testing module comprises a logic testing module, a waveform format controller module, a base pin circuit module and a digital comparing module; the logic testing module receives a main clock signal and a first testing vector and simultaneously sends a second testing vector to the waveform format controller module; the first testing vector is transmitted to the logic testing module and is stored before testing begins; and when testing begins, the logic testing module selects the stored first testing vector, forms and transmits the second testing vector to the waveform format controller module. The testing device intensifies the functions of a tester of the traditional memory so that the tester not only has the powerful testing function of the traditional memory, but also has the testing capability of a complex logic device; and simultaneously the very strong simultaneous testing capability of the tester is beyond that of the traditional logic tester, thereby effectively reducing the testing cost and saving the testing time.

Description

technical field [0001] The invention relates to a test device, in particular to a test device for digital semiconductor devices. The invention also relates to a testing method, especially a testing method for digital semiconductor devices. Background technique [0002] The advantage of the logic tester is that the digital channels are flexible and changeable. The vector generator is in SQPG mode. The generated vectors have high complexity and large vector storage depth. The tester structure is as figure 1 As shown, it mainly consists of pin circuit module (PE module, Pin Electronics), waveform format controller module (TGFC module, Timing Generator Format Control), digital comparison module (SC module, Sense Control), programmable data selector module ( PDS module, Programmable Data Selector), algorithm vector generator module (ALPG module, Algorithmic Pattern Generator) and timing generator module (TG module, Timing Generator) six parts constitute the test hardware module...

AI Technical Summary

Problems solved by technology

The advantage of this memory tester is that it has a large number of digital channels and a large number of simultaneous measurements. The disadvantage is that the vector generator is in ALPG mode, and the generated vector has low complexity and small vector storage depth.

[0003] From this point of view, the two testers have their own characteristics. At present, there are testers that can test memory chips and logic chips at the same time. Generally, SQPG modules are configured in the memory tester, but such a solution The disadvantage of the solution is that many memory testers do not support SQPG. Even if they support it, the cost of installing the plug-in is very high, and the program and vector need to be redeveloped, which will increase additional development costs.

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