Scanning method for non-boundary scanning device

Abstract

The invention discloses a scanning method for a non-boundary scanning device. The description of the non-boundary scanning device is divided into a head section, a declaration section and a main body section, wherein the description format of the head section comprises keywords, numbers or character strings and an end symbol; the declaration section comprises a pin description, a signal description and a connection wire description; a pin is used for describing encapsulation of the non-boundary scanning device; a signal is used for describing a relation between a logic signal of the non-boundary scanning device and the pin; and the description format of the main body section comprises a left expression, operators and a right expression. The scanning method has the beneficial effects that: the description of the non-boundary scanning device is divided into three sections, so that the description is simple, and can be identified and understood by a computer easily; and furthermore, a complicated logic can be described by performing various permutations and combinations on the operators.

Description

technical field [0001] The invention relates to a description method of a non-boundary scan device, which belongs to the field of integrated circuit board-level production testing. Background technique [0002] With the development of integrated circuits into the era of VLSI, the high complexity of circuit boards and multi-layer printed boards, surface mount (SMT), ball grid array (BGA), wafer scale integration (WSI) and multi-chip modules The application of (MCM) technology in the circuit system has made the physical accessibility of circuit nodes gradually weakened or even disappeared, and the testability of circuits and systems has declined sharply. Due to the increasing integration of circuit boards, the distance between nodes available for testing is getting smaller and smaller, and some even completely become recessive nodes. In this case, if only traditional testing methods such as probes and needle beds There are many disadvantages in the device failure test of the ...

AI Technical Summary

Problems solved by technology

[0008] The IBIS model is a fast and accurate modeling method for I / O BUFFER based on the V / I (voltage / current) curve. It is an international standard that reflects the electrical characteristics of the chip driver and receiver. It provides a standard file format to Record parameters such as drive source output impedance, rise / fall time, and input load, which is very suitable for calculation and simulation of high-frequency effects such as oscillation and crosstalk. However, the description of the logic expression required for circuit board testing is weak

[0009] The cluster model is a language developed by American Asset Company to describe non-scanning devices. It can complete the description of simple logic, such as exclusion, AND gate, and NOT gate, but it is difficult to complete the description of complex logic.

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