Video frame rate improving system and frame rate improving method

Abstract

The invention discloses a video frame rate improving system and a frame rate improving method, wherein a video data input control module, a video data cache module and a video data output control module are connected in sequence to form a data path; a plurality of cache regions are arranged in the video data cache module, a frame of data is stored in each cache region, the number of the cache regions is obtained by extracting an integer from the ratio of an output clock of the video data to an input clock of the video data and adding 1, and the ratio can be extracted from any numbers while not being limited within an integer range, thereby expanding the realization range of the video frame rate improvement. Besides, the number of the cache regions is larger than or equal to the ratio of the output clock to the input clock of the video data, so that the number of the cache regions can satisfy the application demand no matter how the ratio is selected, which eliminates the transmission delay of the video images.

Description

technical field [0001] The invention relates to the technical field of video monitoring, in particular to a video frame rate improving system and a frame rate improving method in which a plurality of buffer areas are set in a video data buffer module and the applicable scope of frame rate improvement is expanded. Background technique [0002] figure 1 It is a schematic structural diagram of a double-buffer video frame rate improvement system in the prior art. [0003] In the prior art, the frame rate improvement of video data is currently mostly implemented based on double buffering. The structure of the double buffering video frame rate improving system is shown in the attached figure 1 shown. The principle is that the video data cache module is composed of two buffer areas Buffer1 and Buffer2, and each Buffer can buffer one frame of data respectively. The video data output clock clk_o must be an integer multiple N of the video data input clock clk_i. When the input data ...

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Problems solved by technology

[0004] However, the existing double-buffer video frame rate promotion system has the following disadvantages: 1. The scope of application is narrow, and the data output clock frequency must be an integer multiple of the data input clock frequency, which limits its scope of application; 2. When the multiple N is large , there is a serious hysteresis in the video image

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