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Memory system

A storage system and storage unit technology, applied in the field of storage systems, can solve problems such as data errors, expansion, and write errors

Inactive Publication Date: 2012-05-30
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In recent years, with the miniaturization of NAND flash memory, the influence of interference noise between adjacent cells has increased relatively, and writing errors may occur
In addition, by repeatedly writing and reading NAND flash memory, errors may occur in the data stored in the memory cell.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0031] figure 1 It is a block diagram of a configuration example of SSD 100 as a storage system. The SSD 100 is connected to a host device (hereinafter referred to as host) 1 such as a personal computer or a CPU core through a memory connection interface such as an ATA interface (ATA I / F) 2 , and functions as an external memory of the host 1 . In addition, SSD 100 can transmit and receive data between debugging / manufacturing inspection devices 200 via communication interface 3 such as an RS232C interface (RS232C I / F).

[0032] SSD100 has: NAND type flash memory (hereinafter referred to as NAND memory) 10 as non-volatile semiconductor memory; drive control circuit 4 as controller; DRAM 20 as volatile semiconductor memory; power supply circuit 5; status display LED6 used; temperature sensor 7 to detect the temperature inside the driver; and fuse 8.

[0033] Power supply circuit 5 generates a plurality of different internal DC power supply voltages from an external DC power sup...

no. 2 Embodiment approach

[0126] Next, a second embodiment will be described. In the above-mentioned first embodiment, in order to reduce the influence of PD, RD, and DR, the management table MT is referred to, and the read levels VA, VB, VC and the read voltage Vread are changed in the + direction or the - direction to perform a read operation. After this read operation, ECC is judged, and when the number of error bits is large, the block is refreshed.

[0127] In contrast, the second embodiment performs offset reading (retry reading) when the number of error bits is too large to perform ECC error correction (ECC error) in ECC error correction at the time of initial reading. Moreover, by re-executing the ECC error correction, the defect rate of the system is improved.

[0128] Figure 13 , Figure 14 2nd Embodiment is shown. Such as Figure 13 As shown, first, data is read from a memory cell, for example, by a default read level (S31). Then, it is judged whether ECC error correction is possible ...

no. 3 Embodiment approach

[0145] Figure 15 3rd embodiment is shown. The third embodiment is a read operation in which the first and second embodiments are combined. That is, the monitoring reading described in the first embodiment is executed at power-on or at an arbitrary timing. In contrast, in the third embodiment, when an ECC error occurs during the read operation, the read level is shifted to both + / -, the read operation is performed, and the status data at that time is recorded in the management table. In the next read operation, the read operation is performed based on the state data recorded in the management table.

[0146] Such as Figure 15 As shown, for example, a read operation is performed with a default read level (S51). Then, it is judged whether ECC error correction is possible (S52). If the result of this determination is that an ECC error has occurred, first, for example, the read level is shifted slightly higher, and +offset read is performed (S53). After this reading, it is ...

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Abstract

Disclosed is a memory system provided with: a nonvolatile semiconductor storage device, which has a memory cell array having a plurality of blocks including a plurality of memory cells, and a voltage generating unit which can change the read level of the memory cells,and a control unit which controls write, read and erase of the nonvolatile semiconductor storage device. The control unit changes the read level at the start of using the nonvolatile semiconductor storage device and at a certain time after the start.

Description

technical field [0001] Embodiments of the present invention relate to memory systems employing, for example, NAND-type flash memory. Background technique [0002] As an alternative to hard disk devices, for example, SSDs (Solid State Drives) using NAND-type flash memories have been developed. In recent years, with the progress of miniaturization of NAND flash memory, the influence of interference noise between adjacent cells is relatively increased, and writing errors may occur. In addition, data stored in memory cells may be erroneous due to repeated writing and reading of the NAND flash memory. Therefore, a storage system using a NAND flash memory performs error correction using ECC (Error Correction Code) in order to restore read data. Contents of the invention [0003] The present invention provides a storage system capable of reducing the effects of write disturb, read disturb, and / or deterioration of data retention and improving reliability. [0004] An aspect of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/02G06F12/16G11C16/04G11C16/06
CPCG06F11/1048G11C16/0483G11C16/26G06F2201/88G11C11/5642G11C11/5628G06F11/3466G11C16/34G11C16/06G06F12/16G11C16/14G11C16/24G11C16/3418
Inventor 永岛宏行
Owner KK TOSHIBA
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