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Redundant metal filling method for integrated circuit layout

A redundant metal, integrated circuit technology, applied in the fields of electrical digital data processing, instrumentation, calculation, etc., can solve the problem of increasing interconnect capacitance, signal delay, chroma, brightness, interference, noise, energy consumption, increase in calculation amount, and increase the difficulty of design. and other problems to achieve the effect of reducing the impact of convergence and signal integrity, reducing the impact and improving reliability

Active Publication Date: 2013-07-03
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology

However, redundant metal increases interconnect capacitance, signal delay, chroma-luminance interference noise, and power consumption
At the same time, due to the sharp increase in the amount of calculations, redundant metals also increase the difficulty of design (for example: inspection of design rules, extraction of layout parasitic parameters, optical correction (OPC), etc.)

Method used

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  • Redundant metal filling method for integrated circuit layout
  • Redundant metal filling method for integrated circuit layout
  • Redundant metal filling method for integrated circuit layout

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Embodiment Construction

[0015] In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0016] In integrated circuit manufacturing and layout design, the problem that redundant metals increase the coupling capacitance of signal lines is often encountered.

[0017] Such as figure 1 As shown, a redundant metal 3 with a defined area is filled between the two parallel signal lines 1 and 2 . Since the filling position and filling shape of the redundant metal 3 are not considered, the redundant metal has a great influence on the coupling capacitance between the two signal lines.

[0018] The filling method of the redundant metal in the layout of the integrated circuit disclosed by the present invention fully considers the filling position and filling shape of the redundant metal between the signal lines. In order to achieve t...

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Abstract

The invention discloses a dummy fill insertion method for an integrated circuit layout, and belongs to the technical field of microelectronics. In the dummy fill insertion method, distances between dummy fills and a signal wire are prolonged, the number of the dummy fills is decreased in a direction vertical to the signal wire, the stagger arrangement of the dummy fills is avoided at the same time and the way of arranging the dummy fills is changed, so that the influence of the dummy fills on signal wire coupling capacitance is reduced, and the influence of the dummy fills on the convergence of a time sequence and the integrity of a signal is reduced and the reliability of the product is improved.

Description

technical field [0001] The invention relates to the design and manufacture technology of integrated circuit boards, in particular to a method for filling redundant metal in the layout of integrated circuits. Background technique [0002] Redundant metal filling (Dummy Fill) is a technology used in integrated circuit manufacturing to improve surface planarization. It uses redundant metal to improve the uniformity of layout density and improve the surface after chemical mechanical polishing (CMP). Flatness, reduce dishing, erosion, and improve product reliability and yield. Integrated Circuit (IC) manufacturing technology develops at a speed of doubling the integration level every 18 months according to Moore's Law, but when the feature size of integrated circuits drops below 90 nanometers, IC manufacturing technology encounters unprecedented challenges , the surface unevenness has seriously affected the performance and stability of the device, and redundant metal filling has...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 杨飞陈岚阮文彪李志刚王强周隽雄叶甜春
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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