Manufacture method of shallow trench isolation structure for adjusting stress of isolation oxide by ion implantation

Abstract

The invention discloses a manufacture method of a shallow trench isolation structure for adjusting stress of isolation oxide by ion implantation. The method comprises the following steps of: step a, forming a protection layer on a semiconductor substrate; step b, forming a trench for isolating a PMOS (P-channel Metal Oxide Semiconductor) active region and a NMOS (N-channel Metal Oxide Semiconductor) active region on the semiconductor substrate and the protection layer; step c, forming a filling material layer in the trench, so that the trench is filled with the filling material layer to form a shallow trench isolation structure;step D, removing the excess filling material on the surface of the protection layer. The invention has the beneficial effects that for devices adopting HARP (high aspect ratio process) as shallow trench isolation, the stress of the isolation oxide around the PMOS (P-channel Metal Oxide Semiconductor) is adjusted from tensile to pressing by ion implantation, so that the stress state of the PMOS (P-channel Metal Oxide Semiconductor) trench region is changed and the performance is improved; the process is simple and practicable and the process complexity of selective shallow trench filling can be overcome effectively.

Description

technical field [0001] The invention relates to a method for preparing a shallow trench isolation structure, in particular to a method for preparing a shallow trench isolation structure for ion implantation in the field of semiconductor manufacturing to adjust the stress of isolation oxides. Background technique [0002] Sub-atmospheric pressure chemical vapor deposition (SA-CAD) and high-density plasma chemical vapor deposition (HDP-CVD) processes have been widely used in the semiconductor industry. One of the applications is shallow trench isolation (Shallow Trench Isolation) , STI), which uses high-quality silicon dioxide (SiO2) to isolate the active area (Active Areas, AA). For technology nodes smaller than 90nm, the two CVD technologies show some differences, but SA-CVD has the advantages of strong filling ability, adjustable SiO2 film stress and no damage to the underlying material, making it a 70nm node Preferred STI fill schemes for the following semiconductor dev...

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Problems solved by technology

However, this process requires two chemical mechanical polishing and two void fillings, which is very complicated and the yield is low

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