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Method for identifying graphic connection relationship between units in hierarchical layout verification

A connection relationship and identification method technology, which is applied in the field of identification of graphical connection relationships between units in hierarchical layout verification, can solve problems such as lack of intuition and clarity, high processing complexity, complex relationships, etc., to shield complexity, reduce storage consumption, The effect of reducing the amount of data

Inactive Publication Date: 2012-04-04
北京华大九天科技股份有限公司
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AI Technical Summary

Problems solved by technology

[0004] From the above introduction to the edge-based scan line method, we can see that the smallest unit of data processed by this scan line method is edge data, and there are two disadvantages of using an edge as the smallest processing unit: ① There is a large amount of repeated data, Each point as the start and end needs to be stored in two sides, which is very expensive for the current rapidly expanding layout scale
②The processing complexity is high. The scanning line based on the edge intuitively reflects the relationship between the edges, but what needs to be obtained is the connection relationship between the graphics. The relationship between them is complicated, and it is easy to miss the situation

Method used

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  • Method for identifying graphic connection relationship between units in hierarchical layout verification
  • Method for identifying graphic connection relationship between units in hierarchical layout verification
  • Method for identifying graphic connection relationship between units in hierarchical layout verification

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Embodiment Construction

[0018] figure 1 The overall flow chart of the identification method for the graphical connection relationship between cells in hierarchical layout verification:

[0019] Step (1) Initialize, convert the graphics that need to be identified into connection relationships into orthogonal rectangles, then sort these orthogonal rectangles according to the X value of the lower left vertex, and select the smallest X value as the position of the first scanning line;

[0020] Step (2) Select the rectangle queue newly added to the current scan line according to the X value of the scan line position, that is, the rectangle with the X value of the lower left vertex equal to the X value of the scan line position, until the X value of the lower left vertex of a rectangle is greater than the current scan line Position X value, and at the same time determine the X value of the rectangle to be the position of the next scan line, if all rectangles are processed, the position of the next scan lin...

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Abstract

The invention relates to a method for identifying a graphic connection relationship between units in hierarchical layout verification, and belongs to the field of semiconductor integrated circuit design automation. A high-efficiency solution is provided for identification operation of the connection relationship between graphs of two units in the hierarchical layout verification. Most data in the units of a semiconductor integrated circuit design layout is rectangular units which are orthogonal to a coordinate axis; and the traditional method comprises the following steps of: converting polygons in the units into edges, and identifying the connection relationship between graphic units by an edge-based scanning line method, so that data quantity is doubled and efficiency is low. In order to solve the problem, the scanning line method taking a rectangle as a unit is provided, so that the number of data units is greatly reduced, and operating efficiency is obviously improved.

Description

technical field [0001] The invention discloses a method for identifying the graphic connection relationship between units in hierarchical layout verification, which belongs to the field of semiconductor integrated circuit design automation, and is mainly aimed at the identification operation of the connection relationship between the graphics of two units in hierarchical layout verification. Background technique [0002] Layout verification is an important part of the integrated circuit design process. In the deep sub-micron era, as the design scale gradually increases, the scale of layout data expands rapidly, and verification efficiency becomes one of the bottlenecks in integrated circuit design. Hierarchical layout verification is due to It is highly efficient and has attracted much attention. There are a large number of repeating units in the layout, and the concept of the unit is used in the hierarchical layout verification, and all the repeating units are only verified ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 马海南范永兴于士涛
Owner 北京华大九天科技股份有限公司
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