Memory and sense amplifiers

Abstract

A memory and a sense amplifier, the sense amplifier includes a bit line adjustment unit, the bit line adjustment unit includes: a feedback transistor with a control end, a first end and a second end, the control end of which is connected to a bit line node, and the first The end is connected to a voltage source; an impedance element, one end of which is grounded, and the other end is connected to the second end of the feedback transistor; an adjustment transistor having a control end, a first end and a second end, the control end of which is connected to the second end of the feedback transistor, and the first end Connect to the data line node, and connect the second end to the bit line node. When the precharging ends, the present invention can timely turn off the adjusting transistor by adjusting the bit line adjusting unit and feedback to prevent overcharging.

Description

technical field [0001] The invention relates to a memory circuit, in particular to a memory and a sensitive amplifier. Background technique [0002] Sensitive amplifier (SA, SenseAmplifier) ​​is an important part of the memory, which directly affects the reading speed of the memory. Sense amplifiers sense small signal changes on bit-lines and amplify the small signal changes to obtain data stored on memory cells. Before sensing small signal changes on the bit-line, the bit-line adjustment unit of the sense amplifier will adjust the bit-line voltage to a fixed value, so that the bit-line voltage can be stabilized as soon as possible, and then it can sense a stable voltage when reading. bit line current. [0003] figure 1 It is a circuit diagram of an existing sensitive amplifier of a memory, including: [0004] The precharge unit 11 charges the data line node when the bit line is precharged, including: a precharge transistor mp, whose control terminal (gate) is connected ...

AI Technical Summary

Problems solved by technology

At the end of the bit line precharge, as the voltage of the bit line node VD rises to a predetermined value, the NMOS transistor m4 should be turned on, so that the voltage of the feedback node VC changes from high level to low level, and the adjustment transistor m2 is turned off , but when the voltage of the bit line node VD decreases to a certain extent with the decrease of the operating voltage source VDDQ, the voltage difference between the bit line node VD and the feedback node VC will be smaller than the turn-on voltage of the NMOS transistor m4, and the NMOS transistor m4 is in the off state, so the variable gain amplifier cannot play a feedback role. At this time, the voltage of the feedback node VC is a fixed value VDD, that is, the gate voltage of the adjustment transistor m2 is a fixed value VDD, and the adjustment transistor m2 cannot be turned off. On the one hand, it will cause overcharging, which is unfavorable for reading '1' (that is, the state with current on the bit line); on the other hand, because the adjustment transistor m2 cannot be turned off, it is also unfavorable for reading '0' (that is, the state without current on the bit line).

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