A Configurable Differential Delay Cell Circuit
A unit circuit and differential delay technology, which is applied in the field of differential delay unit circuit structure, can solve the problems of output frequency adjustment range limitation, large design overhead, no multiplexing ability, etc., and achieve area cost reduction, area reduction, and implementation selectivity Effect
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[0019] The circuit structure and working process of the configurable differential delay unit disclosed in the present invention will be described in detail below in conjunction with the accompanying drawings.
[0020] The invention discloses a configurable differential delay unit circuit, which is characterized in that it includes an input selection circuit, an input circuit and a load circuit, specifically composed of PMOS transistors M1, M2, M3, M4, M9, M12, NOMS transistors M5, M6 , M7, M8, M10, M11, M13, M14, M15, M16 and inverters INV1, INV2; the specific feature is that: M5 and M8 form a source coupling pair of tubes, and their gates are respectively connected to differential inputs In1+ and In1- , its drains are respectively connected to the differential outputs Out- and Out+, its source is connected to the drain of M14, the source of M14 is connected to ground, its gate is connected to the source of M10, the drain of M13 and the drain of M9 , the drain of M10 is connec...
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