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Low drop-out voltage regulator with wide bandwidth power supply rejection ratio

A voltage regulator, low dropout technology, applied in the field of integrated circuits, can solve problems such as damage to the performance of analog circuit blocks

Inactive Publication Date: 2011-11-09
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the presence of wide-bandwidth noise on the VDD source voltage, an LDO regulator with such poor PSRR will impair the performance of analog blocks in PLLs, VCOs, DACs, ADCs, and RF transceivers utilizing proper VREG output voltages

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  • Low drop-out voltage regulator with wide bandwidth power supply rejection ratio
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Embodiment Construction

[0024] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0025] Wide bandwidth Power Supply Rejection Ratio (PSRR) Low Dropout (LDO) voltage regulators are noise-sensitive individual analog circuits such as Phase-Locked Loops (PLLs), Voltage-Controlled Oscillators (VCOs), high-speed Digital-to-Analog Converters (DACs) ), reference current generators for high-speed analog-to-digital converters (ADCs), and other wide-bandwidth analog cores) to generate clean voltage supplies. Use of individual wide-bandwidth PSRR LDO regulators for separate analog blocks in the SoC allows on-package supply pumps to be shared between multiple PLLs and other embedded analog cores; thereby reducing the need for on-package supply pumps for noise-sensitive analog circuits Number of.

[0026] Figu...

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Abstract

A low drop-out (LDO) voltage regulator with a wide bandwidth power supply rejection ratio (PSRR) is described. In one aspect, the LDO voltage regulator includes two individual voltage regulator circuit stages. A first stage voltage regulator circuit output is at an intermediate voltage (VINT) between an input supply voltage (VDD) and a final regulated output voltage (VREG). A second stage voltage regulator circuit output is at the final regulated output voltage (VREG) and is optimized for noise-sensitive analog circuits across a wide operating bandwidth. The first stage voltage regulator circuit has a zero frequency while the second stage voltage regulator circuit has a matching pole frequency to minimize the AC response from VDD to VREG across all frequencies.

Description

technical field [0001] The present invention relates generally to the field of integrated circuits and, more particularly, to applications for noise-sensitive individual analog circuits such as phase-locked loops (PLLs) and other embedded analog cores within a system-on-chip (SoC) Low Dropout (LDO) Regulators. Background technique [0002] Embedded analog circuits such as phase-locked loops (PLLs), voltage-controlled oscillators (VCOs), digital-to-analog converters (DACs), analog-to-digital converters (ADCs), and radio-frequency (RF) transceivers rely on wide-bandwidth wireless Noise supply voltage to meet phase noise, timing jitter, spurious-free dynamic range and low-noise figure requirements in individual blocks. [0003] figure 1 is an example integrated circuit die block diagram of SoC 100 utilizing multiple LDOs 110 connected to multiple circuit blocks 120 tied to a common external supply voltage VDD. [0004] As more SoC designs move toward embedding more analog ci...

Claims

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Application Information

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IPC IPC(8): G05F1/56G05F1/575
CPCG05F1/575G05F1/56G05F1/563
Inventor 萨梅尔·瓦德瓦
Owner QUALCOMM INC
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