Formation method for grid structure

Abstract

The invention relates to a formation method for a grid structure, which comprises the following steps: providing a substrate on which a grid dielectric layer, a polycrystalline silicon layer, a first metal layer, a metal nitride layer, a second metal layer and a hard masking film layer are formed; sequentially forming a bottom anti-reflection layer and a photoresist pattern on the surface of the hard masking film layer, wherein the photoresist pattern corresponds to the grid structure; taking the photoresist pattern as a masking film to sequentially etch the bottom anti-reflection layer and the hard masking film layer till the second metal layer is exposed; taking the etched hard masking film layer as the masking film, and adopting Cl2, NF3, O2 as etching gas, wherein the volume ratio of Cl2 and NF3 is less than 2, and sequentially etching the second metal layer, the metal nitride layer and the first metal layer till the polycrystalline silicon layer is exposed. No etched pits and impurities are left on the surface of the grid structure formed by the formation method.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a gate structure forming method. Background technique [0002] At present, VLSI has developed to an integration level of more than 100,000 components per single chip. In addition to requiring new circuit design, new device structure and technology, etc., this circuit must further reduce the number of devices. Geometry. [0003] As the aggregate size decreases, Al and polysilicon, which are usually used as low-resistance gates, have a series of problems. For example, for Al, Al is easy to infiltrate in silicon, so there is a short circuit caused by Al infiltration; for polysilicon In terms of its high resistivity (about 10 3 Ωcm), when the line width is reduced to 1 micron, its time constant RC is relatively large, which will affect the speed of the circuit. [0004] In order to solve this problem, the low-resistance gate formation process has become one of the key ma...

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Problems solved by technology

[0009] The above etching process usually uses CF-containing 4 , Cl and He plasma etching, too strong plasma etching will cause damage to the polysilicon layer when etching the metal silicide layer. After the next step, the process penetrates the gate dielectric layer to form etch pits (Pits) on its surface, and the plasma Weak bulk etching will form some impurities in the polysilicon layer and finally form impurities on the surface of the dielectric layer. The reliability of the gate structure formed by the above plasma etching process is low.

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