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Link interface circuit based on serial data transmission mode

An interface circuit and serial data technology, which is applied in the field of high-speed serial LVDS data transmission, can solve the problems that cannot be changed in real time, and achieve the effects of real-time change of transmission mode and transmission length, independent communication mechanism, and simplified parameter configuration

Active Publication Date: 2011-08-10
安徽芯纪元科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The point-to-point transmission method has been applied in the field of real-time processing. For example, the point-to-point transmission method is used in the tiger shark series processors of ADI, but the company's transmission protocol stipulates that the same transmission must be set at the sending end and the receiving end. The mode and transmission length parameters need to be set the same at the sending end and the receiving end. This setting is agreed in advance and cannot be changed in real time.

Method used

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  • Link interface circuit based on serial data transmission mode
  • Link interface circuit based on serial data transmission mode
  • Link interface circuit based on serial data transmission mode

Examples

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Embodiment Construction

[0040] Such as figure 1 As shown, the link interface circuit based on the serial data transmission method includes the interface circuit of the processor core Link sending end, the processor core Link receiving end interface circuit, and the link between the Link sending end and the Link receiving end link port 8-bit data line LINK_DATA[7:0] and three control lines TR_CLK, IRQ, ACK. Among them, TR_CLK, IRQ and LINK_DATA[7:0] are output from the link port sender to the link port receiver, and the ACK signal is fed back to the link port sender by the link port receiver.

[0041] The interface circuit of the link sending end of the processor core (see figure 2 ), with: DMA transmission control register, channel-associated clock generator, DMA controller, a set of 2*8*32bit ping-pong data cache and 8 parallel-to-serial conversion circuits, outputting 8*1bit serial data. Each DMA controller needs to correctly configure the corresponding DMA control registers according to the pro...

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Abstract

The invention discloses a link interface circuit based on a serial data transmission mode. The link interface circuit comprises an interface circuit at the link transmitting end of a processor kernel, an interface circuit at the link receiving end of the processor kernel, an 8-bit data wire and three control wires which are linked between link ports of the link transmitting end and the link receiving end, a link port associated clock generator for generating a link transmission associated clock, a link port direct memory access (DMA) control register for setting a control signal required by link DAM transmission, a link port DMA controller for generating a time sequence required by a link transmission protocol and accessing an address of an internal memory, a link port pingpang buffer register for storing data needed to be subjected to parallel-to-serial conversion transmission and data needed to be subjected to serial-to-parallel conversion receiving during link transmission, and a parallel-to-serial conversion circuit for outputting serial data of eight channels at the same time; and the link port adopts a transmission protocol that the transmitting end transmits parameters to the receiving end so as to realize link transmission of interfaces between two digital signal processors (DSP).

Description

technical field [0001] The invention relates to a link interface circuit based on a serial data transmission mode, which is used for high-speed serial LVDS data transmission between two DSPs. Background technique [0002] In a system composed of multiple processors, data transmission between processors is generally implemented through various buses or point-to-point transmission. Bus-based data transmission architecture requires bus arbitration between processors because multiple processors share the bus. Bus arbitration is not conducive to real-time processing applications, because after the application program submits the bus application, it must wait for the authorization of the bus arbitration mechanism before occupying the bus for data transmission, and this waiting time is unpredictable for the application program. [0003] Different from the bus transmission mode, the transmission initiation timing of the point-to-point transmission mode is completely controlled by t...

Claims

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Application Information

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IPC IPC(8): G06F13/38
Inventor 汪灏郭二辉洪一
Owner 安徽芯纪元科技有限公司
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