TCP (transmission control protocol) stream based verification method

A verification method and logic verification technology, applied in the field of integrated circuit verification, can solve problems such as inflexible writing of testbench, and achieve the effect of shortening development time and improving design quality

Inactive Publication Date: 2011-06-15
SUGON INFORMATION IND
View PDF3 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Now the general logic test method is to use Verilog language, and object-orien

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • TCP (transmission control protocol) stream based verification method
  • TCP (transmission control protocol) stream based verification method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0013] The technical solution uses systemVerilog language to establish a logic verification platform, including an incentive generator, stream management and stream sorting implementation, and an automatic comparator.

[0014] (1) Generate incentives

[0015] The exciter continuously generates a constrained random network packet structure based on TCP connections, including various abnormal connection situations, and drives logic work.

[0016] (2) Connection management and out-of-order rearrangement

[0017] The connection management module records the connection status, the rearrangement module performs random rearrangement according to the results of the management module, and the automatic comparator saves the results to the desired buffer;

[0018] (3) PCIE simulation model receives logic output results

[0019] PCIE receives the logical output result and saves it in the output result buffer. At the same time, it imitates the behavior of the host, sends commands to eac...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention provides a TCP (transmission control protocol) stream based verification method. An exciter continuously generates constrained random TCP connection based network packet structures comprising various abnormal connection conditions, a logic task is enabled, and an automatic comparator receives a logic output result and saves the logic output result into a logic result buffer zone; a connection management module records connection status, a rearrangement module performs unordered rearrangement according to the result of the management module, and the automatic comparator saves the result into an expected buffer zone; and the automatic comparator automatically compares the result of the result buffer zone and the result of the expected buffer zone to verify whether the logic result is correct. In the invention, comprehensive logic function verification is carried out before board-level test to correct a potential bug, improve the design quality and reduce the project development time.

Description

technical field [0001] The invention relates to the field of integrated circuit verification, in particular to a verification method based on TCP flow. Background technique [0002] Due to the increasing complexity of modern FPGA devices, FPGA designs require the same comprehensive functional verification as ASSPs and ASICs before them. For FPGA designs, ensuring design correctness before actual hardware debugging is still critical to project success. Early detection and elimination of design errors before actual hardware debug will speed up the overall design process, increase the likelihood of on-time release, save costs, and avoid or reduce unnecessary frustration. [0003] Now the general logic test method is to use Verilog language, which cannot be programmed with object-oriented thinking, resulting in inflexible testbench writing. This test platform utilizes the C-like grammatical characteristics of the systemVerilog language to write a test platform flexibly and con...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F11/25
Inventor 纪奎赵喜全窦晓光张英文李静
Owner SUGON INFORMATION IND
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap