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High-speed burst demodulation synchronizing device

A synchronization device, high-speed technology, applied in the direction of the synchronization device, the shaping network in the transmitter/receiver, electrical components, etc., can solve the problems of reducing data transmission efficiency and low transmission efficiency of short burst data packets, and achieve improved data transmission efficiency. Transmission efficiency, easy hardware implementation, and the effect of reducing the probability of false alarms

Active Publication Date: 2011-05-04
NO 54 INST OF CHINA ELECTRONICS SCI & TECH GRP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The usual solution is to insert a preamble with a specific pattern before each burst data packet for clock and carrier synchronization. The preamble as a system overhead reduces data transmission efficiency, and the transmission efficiency is even lower for short burst data packets

Method used

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  • High-speed burst demodulation synchronizing device

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Embodiment Construction

[0020] Reference Figure 1 to Figure 4 , The present invention analog-to-digital converter (A / D) 1, down-conversion unit 2, first to second matched filters 3-1 to 3-2, frame header positioning 4, timing recovery 5, decoding 6; figure 1 As shown, figure 1 It is the electrical principle block diagram of the embodiment of the present invention. figure 1 Connect the line. The function of the analog-to-digital converter (A / D) 1 is to convert the demodulated signal to analog-to-digital; the function of the down-conversion unit 2 is to down-convert the signal, convert the intermediate frequency signal into a low-frequency baseband signal, and use one signal Two channels of information are recovered. The function of the first to second matched filters 3-1 to 3-2 is to filter out the noise and image frequency in the signal, and obtain more accurate information for better demodulation later; the function of frame header positioning 4 is to use Correlation peaks and adaptive thresholds r...

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Abstract

The invention discloses a high-speed burst demodulation synchronizing device, and relates to symbol timing synchronization in burst communication in the communication field. The device comprises an analog-to-digital converter, a down-conversion unit, a first match filter, a second match filter, a timing recovery unit and a decoding unit, as well as a frame header positioning unit. The device realizes carrier synchronization and timing synchronization on the basis of a preferential sequence of a specific pattern rather than a feedback loop, and realizes timing synchronization of symbols by adopting a method of combining symbol sequence energy matching and threshold adaptability. The device has the characteristics of short synchronization time, high efficiency and wide application range, and carries out windowing at the moment of grouping a synchronization sequence by combing the cross-layer optimization design and with the auxiliary complexing.

Description

Technical field [0001] The invention relates to a fast packet synchronization technology for high-speed burst communication occasions, which relates to symbol timing synchronization in burst communication in the communication field, and is particularly suitable for burst data communication system applications with high-speed modulation and demodulation. Background technique [0002] Burst communication is widely used in communication systems such as TDMA systems and wireless ad hoc networks. In these systems, data communication is carried out in bursts, and the information transmission is discontinuous, which determines that it is difficult to achieve carrier synchronization and timing synchronization through a feedback loop in such systems. The usual solution is to insert a preamble with a specific pattern before each burst data packet for clock and carrier synchronization. The preamble is used as a system overhead to reduce the data transmission efficiency. For short burst data...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04W56/00H04L25/03H04L27/26
Inventor 石玉景张永杰卢泳兵
Owner NO 54 INST OF CHINA ELECTRONICS SCI & TECH GRP
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