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Nonvolatile memory and arrangement thereof

A non-volatile, memory technology, applied in the field of non-volatile memory layout, can solve the problems of complex process, high cost, poor component yield, etc., to improve component performance, increase component density, and reduce leakage current Effect

Active Publication Date: 2014-07-02
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the advanced logic process, the process of using double-layer polysilicon non-volatile memory as embedded memory is complex and costly, and the component yield is not good

Method used

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  • Nonvolatile memory and arrangement thereof
  • Nonvolatile memory and arrangement thereof
  • Nonvolatile memory and arrangement thereof

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Experimental program
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Embodiment Construction

[0056] figure 2 It is a schematic top view of a non-volatile memory unit according to an embodiment of the present invention.

[0057] Please refer to figure 2 , the non-volatile memory unit 210 of the present invention is composed of a semiconductor substrate 200, a conductor 240, a plurality of isolation structures 270, a first-type doped well 260, two first ion-doped regions 222, 224 and a second ion-doped impurity region 232.

[0058] A plurality of isolation structures 270 parallel to each other are disposed in the semiconductor substrate 200 , such as shallow trench isolation structures (Shallow Trench Isolation, STI). These isolation structures 270 partition the semiconductor substrate 200 into transistor regions 252 and capacitor regions 262 parallel to each other. The first-type doped well 260 is disposed in the container region 262 and is, for example, an N-type doped well.

[0059] In this embodiment, the semiconductor substrate 200 is, for example, an undoped...

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Abstract

The invention discloses a nonvolatile memory arrangement, which includes a semiconductor substrate, a plurality of first type doping wells, a plurality of second conductors, a plurality of first ion doped regions, a plurality of second ion doped regions, a plurality of work lines and a plurality of bit lines. The semiconductor substrate is provided with a plurality of isolation structures for isolating the semiconductor into a plurality of first transistor regions, a plurality of capacitor regions and a plurality of second transistor regions. Each capacitor area is arranged between the corresponding first transistor region and the second transistor region. The plurality of first type doping wells are respectively arranged in one of the corresponding capacitor. Each second ion doped region is arranged in a first type doping well between the adjacent first conductor and the second conductor, and each second ion doped region, together with a corresponding first capacitor component , forms a first capacitor and, together with the corresponding second conductor component, forms a second capacitor.

Description

technical field [0001] The invention relates to a layout structure of a semiconductor element, and in particular to a layout of a non-volatile memory. Background technique [0002] The non-volatile memory (Non-Volatile Memory, NVM) device has the characteristic that the data stored in the device will not disappear due to the interruption of the power supply, so it has become one of the memory devices commonly used to store data at present. [0003] According to the limitation of the read and write times of the memory, non-volatile memory can be divided into: multi-time programmable memory (MTP memory) with repeatable read and write function and data that can only be provided once There are two types of one-time programmable memory (OTP memory) for writing. In addition, if it is distinguished from the device structure, it can be further divided into: double-poly non-volatile memory and single-poly non-volatile memory. [0004] Since the non-volatile memory is compatible wit...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/115H01L29/92H01L29/06H01L23/528
Inventor 施泓林陈智彬殷珮菁蔡慧芳
Owner UNITED MICROELECTRONICS CORP
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