Chip structure, wafer structure and chip fabrication technique

Abstract

The invention relates to a chip structure, a wafer structure and a chip fabrication technique, wherein the chip structure comprises a substrate and a stress-buffering layer. The substrate is provided with a first surface and a second surface opposite from the first surface. The stress-buffering layer is arranged around the substrate, and is at least positioned on one of the first and the second surfaces of the substrate.

Description

technical field [0001] The present invention relates to a semiconductor structure and a semiconductor manufacturing process, in particular to a chip structure, a wafer structure and a chip manufacturing process. Background technique [0002] Before cutting the wafers produced by the semiconductor integrated circuit manufacturing process, the wafers are usually subjected to a thinning process to reduce the thickness of the wafers. After the wafer goes through the thinning process, the area-to-thickness ratio of the wafer becomes larger, so wafer fragments are prone to occur during the subsequent process of picking and placing the wafer, transporting the wafer by the machine, and cutting the wafer. Therefore, the thinned wafer needs to be adhered to a carrier to be supported by the carrier, which is beneficial to the subsequent manufacturing process. However, the wafer still needs to be removed from the carrier after dicing, and chip fragments are prone to occur during and af...

AI Technical Summary

Problems solved by technology

However, the wafer still needs to be removed from the carrier after dicing, and chip fragments are prone to occur during and after the removal process

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